eg2.vhd

FPGA开发光盘各章节实例的设计工程与源码

--例2． 使用变量和信号得到不同的结果

library IEEE;
use IEEE.std_logic_1164.all;

entity eg2 is
	port (
			a_bus 	: in  std_logic_vector(3 downto 0);
			carryout: out  std_logic
		 );
end entity; 

architecture a of eg2 is 
begin 
   process(a_bus)
       variable tmp:std_logic; --变量的定义
   begin
       tmp := '1';
       for i in 3 downto 0 loop
            tmp := a_bus(i) and tmp; --变量的赋值
       end loop;
       carryout <= tmp;
   end process;
end a;