state_m2.map.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 12:59:37 2007 " "Info: Processing started: Sun Feb 18 12:59:37 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off state_m2 -c state_m2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_m2 -c state_m2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_m2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file state_m2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 state_m2-logic " "Info: Found design unit 1: state_m2-logic" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 state_m2 " "Info: Found entity 1: state_m2" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "state_m2 " "Info: Elaborating entity \"state_m2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|state_m2\|filter 5 " "Info: State machine \"\|state_m2\|filter\" contains 5 states" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|state_m2\|filter " "Info: Selected Auto state machine encoding method for state machine \"\|state_m2\|filter\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|state_m2\|filter " "Info: Encoding result for state machine \"\|state_m2\|filter\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "filter.tap4 " "Info: Encoded state bit \"filter.tap4\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "filter.tap3 " "Info: Encoded state bit \"filter.tap3\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "filter.tap2 " "Info: Encoded state bit \"filter.tap2\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "filter.tap1 " "Info: Encoded state bit \"filter.tap1\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "filter.idle " "Info: Encoded state bit \"filter.idle\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_m2\|filter.idle 00000 " "Info: State \"\|state_m2\|filter.idle\" uses code string \"00000\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_m2\|filter.tap1 00011 " "Info: State \"\|state_m2\|filter.tap1\" uses code string \"00011\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_m2\|filter.tap2 00101 " "Info: State \"\|state_m2\|filter.tap2\" uses code string \"00101\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_m2\|filter.tap3 01001 " "Info: State \"\|state_m2\|filter.tap3\" uses code string \"01001\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_m2\|filter.tap4 10001 " "Info: State \"\|state_m2\|filter.tap4\" uses code string \"10001\"" {  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "state_m2.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_m2/state_m2.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "14 " "Info: Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 12:59:39 2007 " "Info: Processing ended: Sun Feb 18 12:59:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}