state_m2.hier_info

FPGA开发光盘各章节实例的设计工程与源码

|state_m2
clk => filter~5.IN1
reset => filter~6.IN1
nw => filter~0.OUTPUTSELECT
nw => filter~1.OUTPUTSELECT
nw => filter~2.OUTPUTSELECT
nw => filter~3.OUTPUTSELECT
nw => filter~4.OUTPUTSELECT
nw => Selector1.IN3
nw => Selector0.IN2
sel[0] <= sel~1.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= sel~0.DB_MAX_OUTPUT_PORT_TYPE
nxt <= filter.tap4.DB_MAX_OUTPUT_PORT_TYPE
first <= filter.tap1.DB_MAX_OUTPUT_PORT_TYPE