state_m2.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

+-------+--------------+------------+------+-------------+----------+
; N/A   ; None         ; 1.937 ns   ; nw   ; filter.idle ; clk      ;
; N/A   ; None         ; 1.936 ns   ; nw   ; filter.tap1 ; clk      ;
+-------+--------------+------------+------+-------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 7.439 ns   ; filter.tap4 ; sel[0] ; clk        ;
; N/A   ; None         ; 7.044 ns   ; filter.tap3 ; sel[1] ; clk        ;
; N/A   ; None         ; 6.845 ns   ; filter.tap2 ; sel[0] ; clk        ;
; N/A   ; None         ; 6.661 ns   ; filter.tap4 ; nxt    ; clk        ;
; N/A   ; None         ; 6.448 ns   ; filter.tap4 ; sel[1] ; clk        ;
; N/A   ; None         ; 6.429 ns   ; filter.tap1 ; first  ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -1.826 ns ; nw   ; filter.tap1 ; clk      ;
; N/A           ; None        ; -1.827 ns ; nw   ; filter.idle ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 13:00:06 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_m2 -c state_m2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "filter.idle" and destination register "filter.tap1"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.727 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N3; Fanout = 2; REG Node = 'filter.idle'
            Info: 2: + IC(0.408 ns) + CELL(0.319 ns) = 0.727 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'filter.tap1'
            Info: Total cell delay = 0.319 ns ( 43.88 % )
            Info: Total interconnect delay = 0.408 ns ( 56.12 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'filter.tap1'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N3; Fanout = 2; REG Node = 'filter.idle'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "filter.idle" (data pin = "nw", clock pin = "clk") is 1.937 ns
    Info: + Longest pin to register delay is 4.861 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_K22; Fanout = 2; PIN Node = 'nw'
        Info: 2: + IC(3.169 ns) + CELL(0.458 ns) = 4.861 ns; Loc. = LC_X1_Y30_N3; Fanout = 2; REG Node = 'filter.idle'
        Info: Total cell delay = 1.692 ns ( 34.81 % )
        Info: Total interconnect delay = 3.169 ns ( 65.19 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N3; Fanout = 2; REG Node = 'filter.idle'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
Info: tco from clock "clk" to destination pin "sel[0]" through register "filter.tap4" is 7.439 ns
    Info: + Longest clock path from clock "clk" to source register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N4; Fanout = 5; REG Node = 'filter.tap4'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.349 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N4; Fanout = 5; REG Node = 'filter.tap4'
        Info: 2: + IC(0.544 ns) + CELL(0.280 ns) = 0.824 ns; Loc. = LC_X1_Y30_N5; Fanout = 1; COMB Node = 'sel~1'
        Info: 3: + IC(1.121 ns) + CELL(2.404 ns) = 4.349 ns; Loc. = PIN_F17; Fanout = 0; PIN Node = 'sel[0]'
        Info: Total cell delay = 2.684 ns ( 61.72 % )
        Info: Total interconnect delay = 1.665 ns ( 38.28 % )
Info: th for register "filter.tap1" (data pin = "nw", clock pin = "clk") is -1.826 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'filter.tap1'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.860 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_K22; Fanout = 2; PIN Node = 'nw'
        Info: 2: + IC(3.168 ns) + CELL(0.458 ns) = 4.860 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'filter.tap1'
        Info: Total cell delay = 1.692 ns ( 34.81 % )
        Info: Total interconnect delay = 3.168 ns ( 65.19 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 13:00:06 2007
    Info: Elapsed time: 00:00:00