bin2bcd.vht

FPGA开发光盘各章节实例的设计工程与源码

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors     
-- are exported from a vector file in the Quartus Waveform Editor and apply to  
-- the top level entity of the current Quartus project .The user can use this   
-- testbench to simulate his design using a third-party simulation tool .       
-- *****************************************************************************
-- Generated on "02/18/2007 12:56:34"
                                                             
-- Vhdl Test Bench(with test vectors) for design  :          bin2bcd
-- 
-- Simulation tool : 3rd Party
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY bin2bcd_vhd_vec_tst IS
END bin2bcd_vhd_vec_tst;
ARCHITECTURE bin2bcd_arch OF bin2bcd_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL data_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL EN : STD_LOGIC;
COMPONENT bin2bcd
	PORT (
	data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	EN : IN STD_LOGIC
	);
END COMPONENT;
BEGIN
	i1 : bin2bcd
	PORT MAP (
-- list connections between master ports and signals
	data_in => data_in,
	data_out => data_out,
	EN => EN
	);
-- data_in[3]
t_prcs_data_in_3: PROCESS
BEGIN
	FOR i IN 1 TO 6
	LOOP
		data_in(3) <= '0';
		WAIT FOR 80000 ps;
		data_in(3) <= '1';
		WAIT FOR 80000 ps;
	END LOOP;
	data_in(3) <= '0';
WAIT;
END PROCESS t_prcs_data_in_3;
-- data_in[2]
t_prcs_data_in_2: PROCESS
BEGIN
	FOR i IN 1 TO 12
	LOOP
		data_in(2) <= '0';
		WAIT FOR 40000 ps;
		data_in(2) <= '1';
		WAIT FOR 40000 ps;
	END LOOP;
	data_in(2) <= '0';
WAIT;
END PROCESS t_prcs_data_in_2;
-- data_in[1]
t_prcs_data_in_1: PROCESS
BEGIN
LOOP
	data_in(1) <= '0';
	WAIT FOR 20000 ps;
	data_in(1) <= '1';
	WAIT FOR 20000 ps;
	IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_data_in_1;
-- data_in[0]
t_prcs_data_in_0: PROCESS
BEGIN
LOOP
	data_in(0) <= '0';
	WAIT FOR 10000 ps;
	data_in(0) <= '1';
	WAIT FOR 10000 ps;
	IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_data_in_0;

-- EN
t_prcs_EN: PROCESS
BEGIN
	EN <= '0';
	WAIT FOR 190000 ps;
	EN <= '1';
WAIT;
END PROCESS t_prcs_EN;
END bin2bcd_arch;