bin2bcd.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

Classic Timing Analyzer report for bin2bcd
Sun Feb 18 12:53:15 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                              ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From       ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 8.806 ns    ; data_in[1] ; data_out[3] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;            ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------------+-------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F780C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------+
; tpd                                                                    ;
+-------+-------------------+-----------------+------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To          ;
+-------+-------------------+-----------------+------------+-------------+
; N/A   ; None              ; 8.806 ns        ; data_in[1] ; data_out[3] ;
; N/A   ; None              ; 8.794 ns        ; data_in[1] ; data_out[4] ;
; N/A   ; None              ; 8.647 ns        ; data_in[2] ; data_out[3] ;
; N/A   ; None              ; 8.635 ns        ; data_in[2] ; data_out[4] ;
; N/A   ; None              ; 8.610 ns        ; data_in[0] ; data_out[0] ;
; N/A   ; None              ; 8.399 ns        ; data_in[1] ; data_out[1] ;
; N/A   ; None              ; 8.398 ns        ; data_in[1] ; data_out[2] ;
; N/A   ; None              ; 8.267 ns        ; EN         ; data_out[3] ;
; N/A   ; None              ; 8.254 ns        ; EN         ; data_out[4] ;
; N/A   ; None              ; 8.253 ns        ; EN         ; data_out[0] ;
; N/A   ; None              ; 8.240 ns        ; data_in[2] ; data_out[1] ;
; N/A   ; None              ; 8.236 ns        ; data_in[2] ; data_out[2] ;
; N/A   ; None              ; 8.066 ns        ; data_in[3] ; data_out[3] ;
; N/A   ; None              ; 8.053 ns        ; data_in[3] ; data_out[4] ;
; N/A   ; None              ; 7.860 ns        ; EN         ; data_out[1] ;
; N/A   ; None              ; 7.856 ns        ; EN         ; data_out[2] ;
; N/A   ; None              ; 7.659 ns        ; data_in[3] ; data_out[1] ;
; N/A   ; None              ; 7.658 ns        ; data_in[3] ; data_out[2] ;
+-------+-------------------+-----------------+------------+-------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 12:53:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bin2bcd -c bin2bcd --timing_analysis_only
Info: Longest tpd from source pin "data_in[1]" to destination pin "data_out[3]" is 8.806 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_M23; Fanout = 4; PIN Node = 'data_in[1]'
    Info: 2: + IC(3.669 ns) + CELL(0.366 ns) = 5.269 ns; Loc. = LC_X1_Y24_N8; Fanout = 1; COMB Node = 'data_out~93'
    Info: 3: + IC(1.161 ns) + CELL(2.376 ns) = 8.806 ns; Loc. = PIN_L26; Fanout = 0; PIN Node = 'data_out[3]'
    Info: Total cell delay = 3.976 ns ( 45.15 % )
    Info: Total interconnect delay = 4.830 ns ( 54.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 12:53:15 2007
    Info: Elapsed time: 00:00:00