top.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

+-------+--------------+------------+------+-------+----------+
; N/A   ; None         ; 1.988 ns   ; y_in ; y_reg ; clock    ;
; N/A   ; None         ; 1.984 ns   ; w_in ; w_reg ; clock    ;
; N/A   ; None         ; 1.857 ns   ; x_in ; x_reg ; clock    ;
+-------+--------------+------------+------+-------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 6.998 ns   ; z_out~reg0 ; z_out ; clock      ;
+-------+--------------+------------+------------+-------+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -1.747 ns ; x_in ; x_reg ; clock    ;
; N/A           ; None        ; -1.874 ns ; w_in ; w_reg ; clock    ;
; N/A           ; None        ; -1.878 ns ; y_in ; y_reg ; clock    ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 13:18:28 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top -c top --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 422.12 MHz between source register "y_reg" and destination register "z_out~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.840 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'
            Info: 2: + IC(0.382 ns) + CELL(0.458 ns) = 0.840 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'
            Info: Total cell delay = 0.458 ns ( 54.52 % )
            Info: Total interconnect delay = 0.382 ns ( 45.48 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.998 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'
                Info: Total cell delay = 1.370 ns ( 45.70 % )
                Info: Total interconnect delay = 1.628 ns ( 54.30 % )
            Info: - Longest clock path from clock "clock" to source register is 2.998 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'
                Info: Total cell delay = 1.370 ns ( 45.70 % )
                Info: Total interconnect delay = 1.628 ns ( 54.30 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "y_reg" (data pin = "y_in", clock pin = "clock") is 1.988 ns
    Info: + Longest pin to register delay is 4.976 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W14; Fanout = 1; PIN Node = 'y_in'
        Info: 2: + IC(3.666 ns) + CELL(0.223 ns) = 4.976 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'
        Info: Total cell delay = 1.310 ns ( 26.33 % )
        Info: Total interconnect delay = 3.666 ns ( 73.67 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
Info: tco from clock "clock" to destination pin "z_out" through register "z_out~reg0" is 6.998 ns
    Info: + Longest clock path from clock "clock" to source register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.844 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'
        Info: 2: + IC(1.157 ns) + CELL(2.687 ns) = 3.844 ns; Loc. = PIN_AD15; Fanout = 0; PIN Node = 'z_out'
        Info: Total cell delay = 2.687 ns ( 69.90 % )
        Info: Total interconnect delay = 1.157 ns ( 30.10 % )
Info: th for register "x_reg" (data pin = "x_in", clock pin = "clock") is -1.747 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N6; Fanout = 1; REG Node = 'x_reg'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.845 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA15; Fanout = 1; PIN Node = 'x_in'
        Info: 2: + IC(3.673 ns) + CELL(0.085 ns) = 4.845 ns; Loc. = LC_X25_Y1_N6; Fanout = 1; REG Node = 'x_reg'
        Info: Total cell delay = 1.172 ns ( 24.19 % )
        Info: Total interconnect delay = 3.673 ns ( 75.81 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 13:18:29 2007
    Info: Elapsed time: 00:00:01