top.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_TSU_RESULT" "y_reg y_in clock 1.988 ns register " "Info: tsu for register \"y_reg\" (data pin = \"y_in\", clock pin = \"clock\") is 1.988 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.976 ns + Longest pin register " "Info: + Longest pin to register delay is 4.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns y_in 1 PIN PIN_W14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W14; Fanout = 1; PIN Node = 'y_in'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { y_in } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.223 ns) 4.976 ns y_reg 2 REG LC_X25_Y1_N0 1 " "Info: 2: + IC(3.666 ns) + CELL(0.223 ns) = 4.976 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.889 ns" { y_in y_reg } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 26.33 % ) " "Info: Total cell delay = 1.310 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.666 ns ( 73.67 % ) " "Info: Total interconnect delay = 3.666 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { y_in y_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { y_in y_in~out0 y_reg } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.998 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns y_reg 2 REG LC_X25_Y1_N0 1 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N0; Fanout = 1; REG Node = 'y_reg'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { clock y_reg } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock y_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 y_reg } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { y_in y_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { y_in y_in~out0 y_reg } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.223ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock y_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 y_reg } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock z_out z_out~reg0 6.998 ns register " "Info: tco from clock \"clock\" to destination pin \"z_out\" through register \"z_out~reg0\" is 6.998 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.998 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns z_out~reg0 2 REG LC_X25_Y1_N5 1 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { clock z_out~reg0 } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 44 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock z_out~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 z_out~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 44 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.844 ns + Longest register pin " "Info: + Longest register to pin delay is 3.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns z_out~reg0 1 REG LC_X25_Y1_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y1_N5; Fanout = 1; REG Node = 'z_out~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { z_out~reg0 } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 44 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(2.687 ns) 3.844 ns z_out 2 PIN PIN_AD15 0 " "Info: 2: + IC(1.157 ns) + CELL(2.687 ns) = 3.844 ns; Loc. = PIN_AD15; Fanout = 0; PIN Node = 'z_out'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.844 ns" { z_out~reg0 z_out } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.687 ns ( 69.90 % ) " "Info: Total cell delay = 2.687 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 30.10 % ) " "Info: Total interconnect delay = 1.157 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.844 ns" { z_out~reg0 z_out } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.844 ns" { z_out~reg0 z_out } { 0.000ns 1.157ns } { 0.000ns 2.687ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock z_out~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 z_out~reg0 } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.844 ns" { z_out~reg0 z_out } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.844 ns" { z_out~reg0 z_out } { 0.000ns 1.157ns } { 0.000ns 2.687ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "x_reg x_in clock -1.747 ns register " "Info: th for register \"x_reg\" (data pin = \"x_in\", clock pin = \"clock\") is -1.747 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.998 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.542 ns) 2.998 ns x_reg 2 REG LC_X25_Y1_N6 1 " "Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N6; Fanout = 1; REG Node = 'x_reg'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.170 ns" { clock x_reg } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.70 % ) " "Info: Total cell delay = 1.370 ns ( 45.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.628 ns ( 54.30 % ) " "Info: Total interconnect delay = 1.628 ns ( 54.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock x_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 x_reg } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.845 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns x_in 1 PIN PIN_AA15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA15; Fanout = 1; PIN Node = 'x_in'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { x_in } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.673 ns) + CELL(0.085 ns) 4.845 ns x_reg 2 REG LC_X25_Y1_N6 1 " "Info: 2: + IC(3.673 ns) + CELL(0.085 ns) = 4.845 ns; Loc. = LC_X25_Y1_N6; Fanout = 1; REG Node = 'x_reg'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.758 ns" { x_in x_reg } "NODE_NAME" } } { "top.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/s04p10top/top.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.172 ns ( 24.19 % ) " "Info: Total cell delay = 1.172 ns ( 24.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.673 ns ( 75.81 % ) " "Info: Total interconnect delay = 3.673 ns ( 75.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.845 ns" { x_in x_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.845 ns" { x_in x_in~out0 x_reg } { 0.000ns 0.000ns 3.673ns } { 0.000ns 1.087ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.998 ns" { clock x_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.998 ns" { clock clock~out0 x_reg } { 0.000ns 0.000ns 1.628ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.845 ns" { x_in x_reg } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.845 ns" { x_in x_in~out0 x_reg } { 0.000ns 0.000ns 3.673ns } { 0.000ns 1.087ns 0.085ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 13:18:29 2007 " "Info: Processing ended: Sun Feb 18 13:18:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}