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来自「FPGA开发光盘各章节实例的设计工程与源码」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.988 ns
From           : y_in
To             : y_reg
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.998 ns
From           : z_out~reg0
To             : z_out
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.747 ns
From           : x_in
To             : x_reg
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 422.12 MHz ( period = 2.369 ns )
From           : y_reg
To             : z_out~reg0
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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