logic.vhd

来自「FPGA开发光盘各章节实例的设计工程与源码」· VHDL 代码 · 共 22 行

--本例中底层模块的文件名为logic.vhd，其模块名与文件名一致，为logic，代码如下：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY logic IS
	PORT(
			a     : IN std_logic;
			b     : IN std_logic;
			c     : IN std_logic;
			x     : OUT std_logic
		);
END logic;

ARCHITECTURE rtl OF logic IS
BEGIN
	PROCESS (a,b,c)
		BEGIN
	      x<=(a and b) or c;
	END PROCESS;
END rtl;