top.merge.rpt

FPGA开发光盘各章节实例的设计工程与源码

Partition Merge report for top
Sun Feb 18 13:18:04 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Partition Merge Summary
  3. Partition Merge Netlist Types Used
  4. Partition Merge Partition Statistics
  5. Partition Merge Resource Usage Summary
  6. Partition Merge Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Partition Merge Summary                                             ;
+--------------------------+------------------------------------------+
; Partition Merge Status   ; Successful - Sun Feb 18 13:18:04 2007    ;
; Quartus II Version       ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name            ; top                                      ;
; Top-level Entity Name    ; top                                      ;
; Family                   ; Stratix                                  ;
; Total logic elements     ; 4                                        ;
; Total pins               ; 5                                        ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0                                        ;
; DSP block 9-bit elements ; 0                                        ;
; Total PLLs               ; 0                                        ;
; Total DLLs               ; 0                                        ;
+--------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used                                                    ;
+----------------+------------------------+------------------------+--------------------+
; Partition Name ; Netlist Type Used      ; Netlist Type Requested ; Partition Contents ;
+----------------+------------------------+------------------------+--------------------+
; Top            ; Post-Synthesis Netlist ; Post-Synthesis Netlist ;                    ;
+----------------+------------------------+------------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics                                                                                                                                                                                                           ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Partition Name ; Logic Elements ; Input Ports ; Output Ports ; Registered Input Ports ; Registered Output Ports ; Unconnected Input Ports ; Unconnected Output Ports ; Driven Ground Input Ports ; Driven VCC Input Ports ; Partition Contents ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Top            ; 4              ; 4           ; 1            ; 4                      ; 1                       ; N/A                     ; N/A                      ; N/A                       ; N/A                    ;                    ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+


+-----------------------------------------------------+
; Partition Merge Resource Usage Summary              ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 4     ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 3     ;
;     -- Combinational with a register        ; 1     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 4     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 4     ;
; I/O pins                                    ; 5     ;
; Maximum fan-out node                        ; clock ;
; Maximum fan-out                             ; 4     ;
; Total fan-out                               ; 11    ;
; Average fan-out                             ; 1.22  ;
+---------------------------------------------+-------+


+--------------------------+
; Partition Merge Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Partition Merge
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 13:18:03 2007
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off top -c top --merge=on
Info: Using synthesis netlist for partition "Top"
Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found
Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
    Info: Allocated 94 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 13:18:04 2007
    Info: Elapsed time: 00:00:01