state_s3.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_TSU_RESULT" "currentstate.st3 control clock 1.884 ns register " "Info: tsu for register \"currentstate.st3\" (data pin = \"control\", clock pin = \"clock\") is 1.884 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.863 ns + Longest pin register " "Info: + Longest pin to register delay is 4.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns control 1 PIN PIN_T25 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_T25; Fanout = 2; PIN Node = 'control'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { control } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.171 ns) + CELL(0.458 ns) 4.863 ns currentstate.st3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(3.171 ns) + CELL(0.458 ns) = 4.863 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.629 ns" { control currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.692 ns ( 34.79 % ) " "Info: Total cell delay = 1.692 ns ( 34.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.171 ns ( 65.21 % ) " "Info: Total interconnect delay = 3.171 ns ( 65.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.863 ns" { control currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.863 ns" { control control~out0 currentstate.st3 } { 0.000ns 0.000ns 3.171ns } { 0.000ns 1.234ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.989 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.542 ns) 2.989 ns currentstate.st3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.161 ns" { clock currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.83 % ) " "Info: Total cell delay = 1.370 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.619 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.619 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.863 ns" { control currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.863 ns" { control control~out0 currentstate.st3 } { 0.000ns 0.000ns 3.171ns } { 0.000ns 1.234ns 0.458ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock y\[1\] currentstate.st3 7.083 ns register " "Info: tco from clock \"clock\" to destination pin \"y\[1\]\" through register \"currentstate.st3\" is 7.083 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.989 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.542 ns) 2.989 ns currentstate.st3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.161 ns" { clock currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.83 % ) " "Info: Total cell delay = 1.370 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.619 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.619 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.938 ns + Longest register pin " "Info: + Longest register to pin delay is 3.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns currentstate.st3 1 REG LC_X1_Y8_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.280 ns) 0.810 ns y~0 2 COMB LC_X1_Y8_N6 1 " "Info: 2: + IC(0.530 ns) + CELL(0.280 ns) = 0.810 ns; Loc. = LC_X1_Y8_N6; Fanout = 1; COMB Node = 'y~0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { currentstate.st3 y~0 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(2.376 ns) 3.938 ns y\[1\] 3 PIN PIN_V26 0 " "Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.938 ns; Loc. = PIN_V26; Fanout = 0; PIN Node = 'y\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.128 ns" { y~0 y[1] } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.656 ns ( 67.45 % ) " "Info: Total cell delay = 2.656 ns ( 67.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.282 ns ( 32.55 % ) " "Info: Total interconnect delay = 1.282 ns ( 32.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.938 ns" { currentstate.st3 y~0 y[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.938 ns" { currentstate.st3 y~0 y[1] } { 0.000ns 0.530ns 0.752ns } { 0.000ns 0.280ns 2.376ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.938 ns" { currentstate.st3 y~0 y[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.938 ns" { currentstate.st3 y~0 y[1] } { 0.000ns 0.530ns 0.752ns } { 0.000ns 0.280ns 2.376ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "currentstate.st2 control clock -1.773 ns register " "Info: th for register \"currentstate.st2\" (data pin = \"control\", clock pin = \"clock\") is -1.773 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.989 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.542 ns) 2.989 ns currentstate.st2 2 REG LC_X1_Y8_N5 2 " "Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.161 ns" { clock currentstate.st2 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.83 % ) " "Info: Total cell delay = 1.370 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.619 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.619 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st2 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.862 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns control 1 PIN PIN_T25 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_T25; Fanout = 2; PIN Node = 'control'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { control } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.170 ns) + CELL(0.458 ns) 4.862 ns currentstate.st2 2 REG LC_X1_Y8_N5 2 " "Info: 2: + IC(3.170 ns) + CELL(0.458 ns) = 4.862 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.628 ns" { control currentstate.st2 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.692 ns ( 34.80 % ) " "Info: Total cell delay = 1.692 ns ( 34.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.170 ns ( 65.20 % ) " "Info: Total interconnect delay = 3.170 ns ( 65.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.862 ns" { control currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.862 ns" { control control~out0 currentstate.st2 } { 0.000ns 0.000ns 3.170ns } { 0.000ns 1.234ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st2 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.862 ns" { control currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.862 ns" { control control~out0 currentstate.st2 } { 0.000ns 0.000ns 3.170ns } { 0.000ns 1.234ns 0.458ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 13:09:46 2007 " "Info: Processing ended: Sun Feb 18 13:09:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}