state_s3.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 13:09:45 2007 " "Info: Processing started: Sun Feb 18 13:09:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off state_s3 -c state_s3 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_s3 -c state_s3 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } } { "d:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register currentstate.st2 currentstate.st3 422.12 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 422.12 MHz between source register \"currentstate.st2\" and destination register \"currentstate.st3\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.730 ns + Longest register register " "Info: + Longest register to register delay is 0.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns currentstate.st2 1 REG LC_X1_Y8_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { currentstate.st2 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.319 ns) 0.730 ns currentstate.st3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(0.411 ns) + CELL(0.319 ns) = 0.730 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { currentstate.st2 currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.319 ns ( 43.70 % ) " "Info: Total cell delay = 0.319 ns ( 43.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.411 ns ( 56.30 % ) " "Info: Total interconnect delay = 0.411 ns ( 56.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { currentstate.st2 currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { currentstate.st2 currentstate.st3 } { 0.000ns 0.411ns } { 0.000ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.989 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.542 ns) 2.989 ns currentstate.st3 2 REG LC_X1_Y8_N2 3 " "Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.161 ns" { clock currentstate.st3 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.83 % ) " "Info: Total cell delay = 1.370 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.619 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.619 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.989 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clock 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.619 ns) + CELL(0.542 ns) 2.989 ns currentstate.st2 2 REG LC_X1_Y8_N5 2 " "Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.161 ns" { clock currentstate.st2 } "NODE_NAME" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.83 % ) " "Info: Total cell delay = 1.370 ns ( 45.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.619 ns ( 54.17 % ) " "Info: Total interconnect delay = 1.619 ns ( 54.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st2 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st2 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { currentstate.st2 currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { currentstate.st2 currentstate.st3 } { 0.000ns 0.411ns } { 0.000ns 0.319ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st3 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.989 ns" { clock currentstate.st2 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.989 ns" { clock clock~out0 currentstate.st2 } { 0.000ns 0.000ns 1.619ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { currentstate.st3 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { currentstate.st3 } {  } {  } "" } } { "state_s3.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/state_s3/state_s3.vhd" 22 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}