state_s3.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

+-------+--------------+------------+---------+------------------+----------+
; N/A   ; None         ; 1.884 ns   ; control ; currentstate.st3 ; clock    ;
; N/A   ; None         ; 1.883 ns   ; control ; currentstate.st2 ; clock    ;
+-------+--------------+------------+---------+------------------+----------+


+--------------------------------------------------------------------------+
; tco                                                                      ;
+-------+--------------+------------+------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To   ; From Clock ;
+-------+--------------+------------+------------------+------+------------+
; N/A   ; None         ; 7.083 ns   ; currentstate.st3 ; y[1] ; clock      ;
; N/A   ; None         ; 7.063 ns   ; currentstate.st1 ; y[0] ; clock      ;
; N/A   ; None         ; 7.002 ns   ; currentstate.st3 ; y[0] ; clock      ;
; N/A   ; None         ; 6.863 ns   ; currentstate.st2 ; y[1] ; clock      ;
+-------+--------------+------------+------------------+------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+---------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To               ; To Clock ;
+---------------+-------------+-----------+---------+------------------+----------+
; N/A           ; None        ; -1.773 ns ; control ; currentstate.st2 ; clock    ;
; N/A           ; None        ; -1.774 ns ; control ; currentstate.st3 ; clock    ;
+---------------+-------------+-----------+---------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 13:09:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_s3 -c state_s3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 422.12 MHz between source register "currentstate.st2" and destination register "currentstate.st3"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.730 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'
            Info: 2: + IC(0.411 ns) + CELL(0.319 ns) = 0.730 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
            Info: Total cell delay = 0.319 ns ( 43.70 % )
            Info: Total interconnect delay = 0.411 ns ( 56.30 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.989 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
                Info: Total cell delay = 1.370 ns ( 45.83 % )
                Info: Total interconnect delay = 1.619 ns ( 54.17 % )
            Info: - Longest clock path from clock "clock" to source register is 2.989 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'
                Info: Total cell delay = 1.370 ns ( 45.83 % )
                Info: Total interconnect delay = 1.619 ns ( 54.17 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "currentstate.st3" (data pin = "control", clock pin = "clock") is 1.884 ns
    Info: + Longest pin to register delay is 4.863 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_T25; Fanout = 2; PIN Node = 'control'
        Info: 2: + IC(3.171 ns) + CELL(0.458 ns) = 4.863 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
        Info: Total cell delay = 1.692 ns ( 34.79 % )
        Info: Total interconnect delay = 3.171 ns ( 65.21 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
        Info: Total cell delay = 1.370 ns ( 45.83 % )
        Info: Total interconnect delay = 1.619 ns ( 54.17 % )
Info: tco from clock "clock" to destination pin "y[1]" through register "currentstate.st3" is 7.083 ns
    Info: + Longest clock path from clock "clock" to source register is 2.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
        Info: Total cell delay = 1.370 ns ( 45.83 % )
        Info: Total interconnect delay = 1.619 ns ( 54.17 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.938 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N2; Fanout = 3; REG Node = 'currentstate.st3'
        Info: 2: + IC(0.530 ns) + CELL(0.280 ns) = 0.810 ns; Loc. = LC_X1_Y8_N6; Fanout = 1; COMB Node = 'y~0'
        Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.938 ns; Loc. = PIN_V26; Fanout = 0; PIN Node = 'y[1]'
        Info: Total cell delay = 2.656 ns ( 67.45 % )
        Info: Total interconnect delay = 1.282 ns ( 32.55 % )
Info: th for register "currentstate.st2" (data pin = "control", clock pin = "clock") is -1.773 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(1.619 ns) + CELL(0.542 ns) = 2.989 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'
        Info: Total cell delay = 1.370 ns ( 45.83 % )
        Info: Total interconnect delay = 1.619 ns ( 54.17 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.862 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_T25; Fanout = 2; PIN Node = 'control'
        Info: 2: + IC(3.170 ns) + CELL(0.458 ns) = 4.862 ns; Loc. = LC_X1_Y8_N5; Fanout = 2; REG Node = 'currentstate.st2'
        Info: Total cell delay = 1.692 ns ( 34.80 % )
        Info: Total interconnect delay = 3.170 ns ( 65.20 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 13:09:46 2007
    Info: Elapsed time: 00:00:01