test1.vhd

来自「FPGA开发光盘各章节实例的设计工程与源码」· VHDL 代码 · 共 12 行

Entity test1 is
     port(a  : in std_logic;
         b,c : out std_logic
        );
   end test1;

   architecture a of test1 is
     begin
        b <= not(a);
        c <= b;--程序在此行会报错
end a;