start_rtl.map.summary

来自「FPGA开发光盘各章节实例的设计工程与源码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sun Feb 18 12:21:16 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : start_rtl
Top-level Entity Name : start_rtl
Family : Stratix
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge