start_rtl.fit.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 12:21:19 2007 " "Info: Processing started: Sun Feb 18 12:21:19 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off start_rtl -c start_rtl " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off start_rtl -c start_rtl" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "start_rtl EP1S10F780C5 " "Info: Selected device EP1S10F780C5 for design \"start_rtl\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "6 Top " "Info: Previous placement does not exist for 6 of 6 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F780C5ES " "Info: Device EP1S10F780C5ES is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F780C5 " "Info: Device EP1S20F780C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F780C5 " "Info: Device EP1S25F780C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S30F780C5 " "Info: Device EP1S30F780C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S30F780C5_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S30F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S40F780C5 " "Info: Device EP1S40F780C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S40F780C5_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S40F780C5_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ H12 " "Info: Pin ~DATA0~ is reserved at location H12" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 2 " "Warning: No exact pin location assignment(s) for 2 pins of 2 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "carryout " "Info: Pin carryout not assigned to an exact location on the device" {  } { { "start_rtl.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl_prj/start_rtl.vhd" 11 -1 0 } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { carryout } "NODE_NAME" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { carryout } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "start_rtl.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl_prj/start_rtl.vhd" 10 -1 0 } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN R25 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN R25" {  } { { "start_rtl.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl_prj/start_rtl.vhd" 10 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" {  } {  } 1 0 "Start inferring scan chains for DSP blocks" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" {  } {  } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0}