start_rtl.vhd

FPGA开发光盘各章节实例的设计工程与源码

--4.3.4  信号与变量的区别

--例1． 使用变量和信号得到相同的结果

library IEEE;
use IEEE.std_logic_1164.all;

entity start_rtl is
	port (
			clk 	: in  std_logic;
			carryout: out  std_logic
		 );
end entity; 

architecture rtl of start_rtl  is --第一个结构体
signal count : integer range 0 to 7; --信号的定义
begin 
   process(clk)
   begin 
      if (clk'event and clk='1') then 
          count <= count + 1; --信号的赋值
          if(count=0) then
              carryout <= '1';
          else 
              carryout <= '0'; 
          end if;
      end if; 
   end process; 
end rtl;