start_rtl.map.rpt

FPGA开发光盘各章节实例的设计工程与源码

; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                             ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------+
; start_rtl.vhd                    ; yes             ; User VHDL File  ; F:/复件 tijiao/程序及软件/cht04/start_rtl_prj/start_rtl.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 4        ;
;     -- Combinational with no register       ; 0        ;
;     -- Register only                        ; 0        ;
;     -- Combinational with a register        ; 4        ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 0        ;
;     -- 3 input functions                    ; 2        ;
;     -- 2 input functions                    ; 1        ;
;     -- 1 input functions                    ; 1        ;
;     -- 0 input functions                    ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 4        ;
;     -- arithmetic mode                      ; 0        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 4        ;
; I/O pins                                    ; 0        ;
; Maximum fan-out node                        ; count[0] ;
; Maximum fan-out                             ; 4        ;
; Total fan-out                               ; 14       ;
; Average fan-out                             ; 2.33     ;
+---------------------------------------------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |start_rtl                 ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |start_rtl          ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 18 12:21:14 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off start_rtl -c start_rtl
Info: Found 2 design units, including 1 entities, in source file start_rtl.vhd
    Info: Found design unit 1: start_rtl-rtl
    Info: Found entity 1: start_rtl
Info: Elaborating entity "start_rtl" for the top level hierarchy
Info: Implemented 6 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Sun Feb 18 12:21:16 2007
    Info: Elapsed time: 00:00:02