start_rtl1.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[0\] count\[2\] 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"count\[0\]\" and destination register \"count\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.884 ns + Longest register register " "Info: + Longest register to register delay is 0.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC_X41_Y30_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N6; Fanout = 4; REG Node = 'count\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.458 ns) 0.884 ns count\[2\] 2 REG LC_X41_Y30_N0 2 " "Info: 2: + IC(0.426 ns) + CELL(0.458 ns) = 0.884 ns; Loc. = LC_X41_Y30_N0; Fanout = 2; REG Node = 'count\[2\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { count[0] count[2] } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.458 ns ( 51.81 % ) " "Info: Total cell delay = 0.458 ns ( 51.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.426 ns ( 48.19 % ) " "Info: Total interconnect delay = 0.426 ns ( 48.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { count[0] count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.884 ns" { count[0] count[2] } { 0.000ns 0.426ns } { 0.000ns 0.458ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns count\[2\] 2 REG LC_X41_Y30_N0 2 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N0; Fanout = 2; REG Node = 'count\[2\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.044 ns" { clk count[2] } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.872 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns count\[0\] 2 REG LC_X41_Y30_N6 4 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N6; Fanout = 4; REG Node = 'count\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.044 ns" { clk count[0] } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { count[0] count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.884 ns" { count[0] count[2] } { 0.000ns 0.426ns } { 0.000ns 0.458ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk count[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[2] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { count[2] } {  } {  } "" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk carryout carryout~reg0 6.593 ns register " "Info: tco from clock \"clk\" to destination pin \"carryout\" through register \"carryout~reg0\" is 6.593 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.872 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_R25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_R25; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns carryout~reg0 2 REG LC_X41_Y30_N5 1 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N5; Fanout = 1; REG Node = 'carryout~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.044 ns" { clk carryout~reg0 } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk carryout~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 carryout~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.565 ns + Longest register pin " "Info: + Longest register to pin delay is 3.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns carryout~reg0 1 REG LC_X41_Y30_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N5; Fanout = 1; REG Node = 'carryout~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { carryout~reg0 } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(2.404 ns) 3.565 ns carryout 2 PIN PIN_G10 0 " "Info: 2: + IC(1.161 ns) + CELL(2.404 ns) = 3.565 ns; Loc. = PIN_G10; Fanout = 0; PIN Node = 'carryout'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.565 ns" { carryout~reg0 carryout } "NODE_NAME" } } { "start_rtl1.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/start_rtl1_prj/start_rtl1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.43 % ) " "Info: Total cell delay = 2.404 ns ( 67.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.161 ns ( 32.57 % ) " "Info: Total interconnect delay = 1.161 ns ( 32.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.565 ns" { carryout~reg0 carryout } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.565 ns" { carryout~reg0 carryout } { 0.000ns 1.161ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk carryout~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 carryout~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.565 ns" { carryout~reg0 carryout } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.565 ns" { carryout~reg0 carryout } { 0.000ns 1.161ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 12:25:41 2007 " "Info: Processing ended: Sun Feb 18 12:25:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}