t_procedure.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "ITDB_TSU_RESULT" "C~reg0 A clk 2.323 ns register " "Info: tsu for register \"C~reg0\" (data pin = \"A\", clock pin = \"clk\") is 2.323 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.087 ns + Longest pin register " "Info: + Longest pin to register delay is 5.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns A 1 PIN PIN_AC11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC11; Fanout = 1; PIN Node = 'A'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.681 ns) + CELL(0.319 ns) 5.087 ns C~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(3.681 ns) + CELL(0.319 ns) = 5.087 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { A C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns ( 27.64 % ) " "Info: Total cell delay = 1.406 ns ( 27.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.681 ns ( 72.36 % ) " "Info: Total interconnect delay = 3.681 ns ( 72.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { A C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.087 ns" { A A~out0 C~reg0 } { 0.000ns 0.000ns 3.681ns } { 0.000ns 1.087ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_AC10 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.542 ns) 2.774 ns C~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { clk C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 58.72 % ) " "Info: Total cell delay = 1.629 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 41.28 % ) " "Info: Total interconnect delay = 1.145 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { A C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.087 ns" { A A~out0 C~reg0 } { 0.000ns 0.000ns 3.681ns } { 0.000ns 1.087ns 0.319ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk C C~reg0 6.493 ns register " "Info: tco from clock \"clk\" to destination pin \"C\" through register \"C~reg0\" is 6.493 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_AC10 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.542 ns) 2.774 ns C~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { clk C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 58.72 % ) " "Info: Total cell delay = 1.629 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 41.28 % ) " "Info: Total interconnect delay = 1.145 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.563 ns + Longest register pin " "Info: + Longest register to pin delay is 3.563 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns C~reg0 1 REG LC_X33_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(2.404 ns) 3.563 ns C 2 PIN PIN_W11 0 " "Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_W11; Fanout = 0; PIN Node = 'C'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.563 ns" { C~reg0 C } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.47 % ) " "Info: Total cell delay = 2.404 ns ( 67.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 32.53 % ) " "Info: Total interconnect delay = 1.159 ns ( 32.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.563 ns" { C~reg0 C } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.563 ns" { C~reg0 C } { 0.000ns 1.159ns } { 0.000ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.563 ns" { C~reg0 C } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.563 ns" { C~reg0 C } { 0.000ns 1.159ns } { 0.000ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "C~reg0 A clk -2.213 ns register " "Info: th for register \"C~reg0\" (data pin = \"A\", clock pin = \"clk\") is -2.213 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_AC10 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.542 ns) 2.774 ns C~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { clk C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 58.72 % ) " "Info: Total cell delay = 1.629 ns ( 58.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 41.28 % ) " "Info: Total interconnect delay = 1.145 ns ( 41.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.087 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns A 1 PIN PIN_AC11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC11; Fanout = 1; PIN Node = 'A'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.681 ns) + CELL(0.319 ns) 5.087 ns C~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(3.681 ns) + CELL(0.319 ns) = 5.087 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { A C~reg0 } "NODE_NAME" } } { "t_procedure.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/t_procedure/t_procedure.vhd" 26 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns ( 27.64 % ) " "Info: Total cell delay = 1.406 ns ( 27.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.681 ns ( 72.36 % ) " "Info: Total interconnect delay = 3.681 ns ( 72.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { A C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.087 ns" { A A~out0 C~reg0 } { 0.000ns 0.000ns 3.681ns } { 0.000ns 1.087ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk clk~out0 C~reg0 } { 0.000ns 0.000ns 1.145ns } { 0.000ns 1.087ns 0.542ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.087 ns" { A C~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.087 ns" { A A~out0 C~reg0 } { 0.000ns 0.000ns 3.681ns } { 0.000ns 1.087ns 0.319ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 13:57:12 2007 " "Info: Processing ended: Sun Feb 18 13:57:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}