t_procedure.fit.summary

FPGA开发光盘各章节实例的设计工程与源码

Fitter Status : Successful - Sun Feb 18 13:57:00 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : t_procedure
Top-level Entity Name : t_procedure
Family : Stratix
Device : EP1S10F780C5
Timing Models : Final
Total logic elements : 1 / 10,570 ( < 1 % )
Total pins : 3 / 427 ( < 1 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )