tst_mult.tan.rpt

FPGA开发光盘各章节实例的设计工程与源码

Classic Timing Analyzer report for tst_mult
Sun Feb 18 13:24:01 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                     ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.112 ns   ; a[0] ; q_out[1] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F780C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-----------------+------+-----------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From ; To        ;
+-----------------------------------------+-----------------------------------------------------+-----------------+------+-----------+
; N/A                                     ; None                                                ; 13.112 ns       ; a[0] ; q_out[1]  ;
; N/A                                     ; None                                                ; 13.109 ns       ; a[0] ; q_out[14] ;
; N/A                                     ; None                                                ; 13.097 ns       ; a[6] ; q_out[1]  ;
; N/A                                     ; None                                                ; 13.094 ns       ; a[6] ; q_out[14] ;
; N/A                                     ; None                                                ; 13.074 ns       ; a[0] ; q_out[3]  ;
; N/A                                     ; None                                                ; 13.059 ns       ; a[6] ; q_out[3]  ;
; N/A                                     ; None                                                ; 13.056 ns       ; a[1] ; q_out[1]  ;
; N/A                                     ; None                                                ; 13.054 ns       ; a[0] ; q_out[5]  ;
; N/A                                     ; None                                                ; 13.053 ns       ; a[1] ; q_out[14] ;
; N/A                                     ; None                                                ; 13.045 ns       ; a[7] ; q_out[1]  ;
; N/A                                     ; None                                                ; 13.042 ns       ; a[7] ; q_out[14] ;
; N/A                                     ; None                                                ; 13.041 ns       ; a[0] ; q_out[13] ;
; N/A                                     ; None                                                ; 13.041 ns       ; a[0] ; q_out[2]  ;
; N/A                                     ; None                                                ; 13.039 ns       ; a[6] ; q_out[5]  ;
; N/A                                     ; None                                                ; 13.026 ns       ; a[6] ; q_out[13] ;
; N/A                                     ; None                                                ; 13.026 ns       ; a[6] ; q_out[2]  ;
; N/A                                     ; None                                                ; 13.018 ns       ; a[1] ; q_out[3]  ;
; N/A                                     ; None                                                ; 13.016 ns       ; a[0] ; q_out[7]  ;
; N/A                                     ; None                                                ; 13.012 ns       ; a[0] ; q_out[9]  ;
; N/A                                     ; None                                                ; 13.010 ns       ; b[2] ; q_out[1]  ;
; N/A                                     ; None                                                ; 13.007 ns       ; b[2] ; q_out[14] ;
; N/A                                     ; None                                                ; 13.007 ns       ; a[7] ; q_out[3]  ;
; N/A                                     ; None                                                ; 13.001 ns       ; a[6] ; q_out[7]  ;
; N/A                                     ; None                                                ; 12.998 ns       ; a[1] ; q_out[5]  ;
; N/A                                     ; None                                                ; 12.997 ns       ; a[6] ; q_out[9]  ;
; N/A                                     ; None                                                ; 12.987 ns       ; a[7] ; q_out[5]  ;