📄 tst_mult.map.rpt
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; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; I/O pins ; 0 ;
; DSP block 9-bit elements ; 1 ;
; Maximum fan-out node ; lpm_mult:u1|mult_p2o:auto_generated|result[0] ;
; Maximum fan-out ; 16 ;
; Total fan-out ; 33 ;
; Average fan-out ; 0.97 ;
+---------------------------------------------+-----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------+
; |tst_mult ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |tst_mult ;
; |lpm_mult:u1| ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |tst_mult|lpm_mult:u1 ;
; |mult_p2o:auto_generated| ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |tst_mult|lpm_mult:u1|mult_p2o:auto_generated ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+----------------------------------+-------------+
; Statistic ; Number Used ;
+----------------------------------+-------------+
; Simple Multipliers (9-bit) ; 1 ;
; Simple Multipliers (18-bit) ; 0 ;
; Simple Multipliers (36-bit) ; 0 ;
; Multiply Accumulators (18-bit) ; 0 ;
; Two-Multipliers Adders (9-bit) ; 0 ;
; Two-Multipliers Adders (18-bit) ; 0 ;
; Four-Multipliers Adders (9-bit) ; 0 ;
; Four-Multipliers Adders (18-bit) ; 0 ;
; DSP Blocks ; -- ;
; DSP Block 9-bit Elements ; 1 ;
; Signed Multipliers ; 0 ;
; Unsigned Multipliers ; 1 ;
; Mixed Sign Multipliers ; 0 ;
; Variable Sign Multipliers ; 0 ;
; Dedicated Shift Register Chains ; 0 ;
+----------------------------------+-------------+
Note: number of DSP Blocks used is only available after a successful fit.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LPM_MULT:u1 ;
+------------------------------------------------+----------+---------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+----------+---------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 8 ; Signed Integer ;
; LPM_WIDTHB ; 8 ; Signed Integer ;
; LPM_WIDTHP ; 16 ; Signed Integer ;
; LPM_WIDTHR ; 0 ; Untyped ;
; LPM_WIDTHS ; 16 ; Signed Integer ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Signed Integer ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Stratix ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_p2o ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
+------------------------------------------------+----------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+-------------+
; Name ; Value ;
+---------------------------------------+-------------+
; Number of entity instances ; 1 ;
; Entity Instance ; LPM_MULT:u1 ;
; -- LPM_WIDTHA ; 8 ;
; -- LPM_WIDTHB ; 8 ;
; -- LPM_WIDTHP ; 16 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+-------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sun Feb 18 13:23:30 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tst_mult -c tst_mult
Info: Found 2 design units, including 1 entities, in source file tst_mult.vhd
Info: Found design unit 1: tst_mult-behavior
Info: Found entity 1: tst_mult
Info: Elaborating entity "tst_mult" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/61/quartus/libraries/megafunctions/LPM_MULT.tdf
Info: Found entity 1: lpm_mult
Info: Elaborating entity "LPM_MULT" for hierarchy "LPM_MULT:u1"
Info: Elaborated megafunction instantiation "LPM_MULT:u1"
Info: Found 1 design units, including 1 entities, in source file db/mult_p2o.tdf
Info: Found entity 1: mult_p2o
Info: Elaborating entity "mult_p2o" for hierarchy "LPM_MULT:u1|mult_p2o:auto_generated"
Info: Implemented 33 device resources after synthesis - the final resource count might be different
Info: Implemented 16 input pins
Info: Implemented 16 output pins
Info: Implemented 1 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Allocated 136 megabytes of memory during processing
Info: Processing ended: Sun Feb 18 13:23:33 2007
Info: Elapsed time: 00:00:03
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