tst_mult.fit.summary

FPGA开发光盘各章节实例的设计工程与源码

Fitter Status : Successful - Sun Feb 18 13:23:48 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : tst_mult
Top-level Entity Name : tst_mult
Family : Stratix
Device : EP1S10F780C5
Timing Models : Final
Total logic elements : 0 / 10,570 ( 0 % )
Total pins : 32 / 427 ( 7 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 1 / 48 ( 2 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )