bin27seg.map.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 12:42:56 2007 " "Info: Processing started: Sun Feb 18 12:42:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bin27seg -c bin27seg " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bin27seg -c bin27seg" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bin27seg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bin27seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bin27seg-bin27seg_arch " "Info: Found design unit 1: bin27seg-bin27seg_arch" {  } { { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bin27seg " "Info: Found entity 1: bin27seg" {  } { { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bin27seg_vhd_vec_tst.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bin27seg_vhd_vec_tst.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bin27seg_vhd_vec_tst-bin27seg_arch " "Info: Found design unit 1: bin27seg_vhd_vec_tst-bin27seg_arch" {  } { { "bin27seg_vhd_vec_tst.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg_vhd_vec_tst.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bin27seg_vhd_vec_tst " "Info: Found entity 1: bin27seg_vhd_vec_tst" {  } { { "bin27seg_vhd_vec_tst.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg_vhd_vec_tst.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "bin27seg " "Info: Elaborating entity \"bin27seg\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 12:42:58 2007 " "Info: Processing ended: Sun Feb 18 12:42:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}