bin27seg.tan.qmsg

FPGA开发光盘各章节实例的设计工程与源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 18 12:43:24 2007 " "Info: Processing started: Sun Feb 18 12:43:24 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off bin27seg -c bin27seg --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bin27seg -c bin27seg --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data_in\[3\] data_out\[4\] 9.868 ns Longest " "Info: Longest tpd from source pin \"data_in\[3\]\" to destination pin \"data_out\[4\]\" is 9.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns data_in\[3\] 1 PIN PIN_G27 7 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G27; Fanout = 7; PIN Node = 'data_in\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[3] } "NODE_NAME" } } { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.961 ns) + CELL(0.183 ns) 5.378 ns Mux2~10 2 COMB LC_X17_Y30_N9 1 " "Info: 2: + IC(3.961 ns) + CELL(0.183 ns) = 5.378 ns; Loc. = LC_X17_Y30_N9; Fanout = 1; COMB Node = 'Mux2~10'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.144 ns" { data_in[3] Mux2~10 } "NODE_NAME" } } { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.183 ns) 6.337 ns data_out~32 3 COMB LC_X19_Y30_N2 1 " "Info: 3: + IC(0.776 ns) + CELL(0.183 ns) = 6.337 ns; Loc. = LC_X19_Y30_N2; Fanout = 1; COMB Node = 'data_out~32'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.959 ns" { Mux2~10 data_out~32 } "NODE_NAME" } } { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.127 ns) + CELL(2.404 ns) 9.868 ns data_out\[4\] 4 PIN PIN_K19 0 " "Info: 4: + IC(1.127 ns) + CELL(2.404 ns) = 9.868 ns; Loc. = PIN_K19; Fanout = 0; PIN Node = 'data_out\[4\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.531 ns" { data_out~32 data_out[4] } "NODE_NAME" } } { "bin27seg.vhd" "" { Text "F:/复件 tijiao/程序及软件/cht04/bin27seg/bin27seg.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.004 ns ( 40.58 % ) " "Info: Total cell delay = 4.004 ns ( 40.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.864 ns ( 59.42 % ) " "Info: Total interconnect delay = 5.864 ns ( 59.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.868 ns" { data_in[3] Mux2~10 data_out~32 data_out[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.868 ns" { data_in[3] data_in[3]~out0 Mux2~10 data_out~32 data_out[4] } { 0.000ns 0.000ns 3.961ns 0.776ns 1.127ns } { 0.000ns 1.234ns 0.183ns 0.183ns 2.404ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 18 12:43:25 2007 " "Info: Processing ended: Sun Feb 18 12:43:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}