📄 nco.rpt
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- 4 - B 22 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|pcarry3
- 4 - B 14 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|pcarry4
- 6 - B 20 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|pcarry5
- 4 - B 13 AND2 0 2 0 1 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|:114
- 1 - B 20 OR2 0 4 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|:162
- 8 - B 20 OR2 0 2 0 1 |phasea:U_phasea|lpm_add_sub:lpm_add_1|:147
- 6 - B 15 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry0
- 8 - B 15 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry1
- 5 - B 21 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry2
- 7 - B 21 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry3
- 4 - B 21 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry4
- 3 - B 17 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|pcarry5
- 6 - B 17 OR2 0 4 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_2|addcore:adder|:162
- 5 - B 17 OR2 0 2 0 1 |phasea:U_phasea|lpm_add_sub:lpm_add_2|:147
- 7 - C 16 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry0
- 4 - C 16 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry1
- 4 - C 19 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry2
- 7 - C 19 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry3
- 2 - C 19 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry4
- 3 - C 20 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|pcarry5
- 6 - C 20 OR2 0 4 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_3|addcore:adder|:162
- 5 - C 20 OR2 0 2 0 1 |phasea:U_phasea|lpm_add_sub:lpm_add_3|:147
- 7 - A 18 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry0
- 2 - A 18 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry1
- 1 - A 01 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry2
- 5 - A 01 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry3
- 2 - A 01 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry4
- 6 - A 05 OR2 0 3 0 2 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry5
- 7 - A 05 OR2 0 3 0 1 |phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder|pcarry6
- 2 - B 15 DFFE + 1 1 0 2 |phasea:U_phasea|pipe17 (|phasea:U_phasea|:45)
- 7 - B 20 DFFE + 1 2 0 1 |phasea:U_phasea|pipe16 (|phasea:U_phasea|:46)
- 3 - B 20 DFFE + 1 2 0 1 |phasea:U_phasea|pipe15 (|phasea:U_phasea|:47)
- 3 - B 14 DFFE + 1 2 0 1 |phasea:U_phasea|pipe14 (|phasea:U_phasea|:48)
- 8 - B 22 DFFE + 1 2 0 1 |phasea:U_phasea|pipe13 (|phasea:U_phasea|:49)
- 6 - B 22 DFFE + 1 2 0 1 |phasea:U_phasea|pipe12 (|phasea:U_phasea|:50)
- 2 - B 22 DFFE + 1 2 0 1 |phasea:U_phasea|pipe11 (|phasea:U_phasea|:51)
- 6 - B 13 DFFE + 1 1 0 2 |phasea:U_phasea|pipe10 (|phasea:U_phasea|:52)
- 7 - B 17 DFFE + 1 1 0 2 |phasea:U_phasea|pipe27 (|phasea:U_phasea|:71)
- 4 - B 17 DFFE + 1 2 0 1 |phasea:U_phasea|pipe26 (|phasea:U_phasea|:72)
- 2 - B 17 DFFE + 1 2 0 1 |phasea:U_phasea|pipe25 (|phasea:U_phasea|:73)
- 8 - B 21 DFFE + 1 2 0 1 |phasea:U_phasea|pipe24 (|phasea:U_phasea|:74)
- 6 - B 21 DFFE + 1 2 0 1 |phasea:U_phasea|pipe23 (|phasea:U_phasea|:75)
- 2 - B 21 DFFE + 1 2 0 1 |phasea:U_phasea|pipe22 (|phasea:U_phasea|:76)
- 7 - B 15 DFFE + 1 2 0 1 |phasea:U_phasea|pipe21 (|phasea:U_phasea|:77)
- 1 - B 15 DFFE + 1 2 0 1 |phasea:U_phasea|pipe20 (|phasea:U_phasea|:78)
- 3 - B 15 DFFE + 1 3 0 2 |phasea:U_phasea|pipec1 (|phasea:U_phasea|:88)
- 7 - C 20 DFFE + 1 1 0 2 |phasea:U_phasea|pipe37 (|phasea:U_phasea|:97)
- 4 - C 20 DFFE + 1 2 0 1 |phasea:U_phasea|pipe36 (|phasea:U_phasea|:98)
- 2 - C 20 DFFE + 1 2 0 1 |phasea:U_phasea|pipe35 (|phasea:U_phasea|:99)
- 8 - C 19 DFFE + 1 2 0 1 |phasea:U_phasea|pipe34 (|phasea:U_phasea|:100)
- 5 - C 19 DFFE + 1 2 0 1 |phasea:U_phasea|pipe33 (|phasea:U_phasea|:101)
- 3 - C 19 DFFE + 1 2 0 1 |phasea:U_phasea|pipe32 (|phasea:U_phasea|:102)
- 8 - C 16 DFFE + 1 2 0 1 |phasea:U_phasea|pipe31 (|phasea:U_phasea|:103)
- 3 - C 16 DFFE + 1 2 0 1 |phasea:U_phasea|pipe30 (|phasea:U_phasea|:104)
- 1 - B 17 DFFE + 1 3 0 2 |phasea:U_phasea|pipec2 (|phasea:U_phasea|:114)
- 1 - A 05 DFFE + 1 2 1 2 |phasea:U_phasea|pipe47 (|phasea:U_phasea|:123)
- 8 - A 05 DFFE + 1 2 0 4 |phasea:U_phasea|pipe46 (|phasea:U_phasea|:124)
- 2 - A 05 DFFE + 1 2 0 3 |phasea:U_phasea|pipe45 (|phasea:U_phasea|:125)
- 8 - A 01 DFFE + 1 2 0 3 |phasea:U_phasea|pipe44 (|phasea:U_phasea|:126)
- 6 - A 01 DFFE + 1 2 0 3 |phasea:U_phasea|pipe43 (|phasea:U_phasea|:127)
- 4 - A 01 DFFE + 1 2 0 3 |phasea:U_phasea|pipe42 (|phasea:U_phasea|:128)
- 4 - A 18 DFFE + 1 2 0 3 |phasea:U_phasea|pipe41 (|phasea:U_phasea|:129)
- 3 - A 18 DFFE + 1 2 0 4 |phasea:U_phasea|pipe40 (|phasea:U_phasea|:130)
- 1 - C 20 DFFE + 1 3 0 2 |phasea:U_phasea|pipec3 (|phasea:U_phasea|:140)
- 6 - A 12 OR2 0 2 1 0 |phasea:U_phasea|:1018
- 8 - A 18 OR2 0 4 0 2 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry1
- 1 - A 04 OR2 0 3 0 2 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry2
- 4 - A 03 OR2 0 3 0 2 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry3
- 8 - A 03 OR2 0 3 0 2 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry4
- 6 - A 02 OR2 0 3 0 2 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry5
- 7 - A 02 OR2 0 3 0 1 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|pcarry6
- 5 - A 14 AND2 0 2 0 1 |phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|:114
- 8 - A 02 DFFE + 1 3 1 2 |phasemod:U_phasemod|mphsreg7 (|phasemod:U_phasemod|:39)
- 4 - A 02 DFFE + 1 3 0 7 |phasemod:U_phasemod|mphsreg6 (|phasemod:U_phasemod|:40)
- 1 - A 02 DFFE + 1 3 0 1 |phasemod:U_phasemod|mphsreg5 (|phasemod:U_phasemod|:41)
- 5 - A 03 DFFE + 1 3 0 1 |phasemod:U_phasemod|mphsreg4 (|phasemod:U_phasemod|:42)
- 7 - A 03 DFFE + 1 3 0 1 |phasemod:U_phasemod|mphsreg3 (|phasemod:U_phasemod|:43)
- 7 - A 04 DFFE + 1 3 0 1 |phasemod:U_phasemod|mphsreg2 (|phasemod:U_phasemod|:44)
- 7 - A 14 DFFE + 1 3 0 1 |phasemod:U_phasemod|mphsreg1 (|phasemod:U_phasemod|:45)
- 1 - A 18 DFFE + 1 2 0 1 |phasemod:U_phasemod|mphsreg0 (|phasemod:U_phasemod|:46)
- 5 - A 04 OR2 0 2 1 0 |phasemod:U_phasemod|:263
- 6 - A 24 AND2 0 2 0 1 |sinlup:U_sinlup|LPM_ADD_SUB:470|addcore:adder|:121
- 1 - A 24 AND2 0 3 0 4 |sinlup:U_sinlup|LPM_ADD_SUB:470|addcore:adder|:125
- 4 - A 22 AND2 0 2 0 1 |sinlup:U_sinlup|LPM_ADD_SUB:470|addcore:adder|:129
- 6 - A 22 AND2 0 3 0 1 |sinlup:U_sinlup|LPM_ADD_SUB:470|addcore:adder|:133
- 7 - A 22 AND2 0 4 0 1 |sinlup:U_sinlup|LPM_ADD_SUB:470|addcore:adder|:137
- - 2 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_0
- - 1 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_1
- - 3 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_2
- - 5 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_3
- - 4 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_4
- - 7 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_5
- - 6 A -- MEM_SGMT 0 6 0 1 |sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_6
- 4 - A 08 DFFE + 1 1 1 0 |sinlup:U_sinlup|:11
- 5 - A 22 DFFE + 1 3 1 0 |sinlup:U_sinlup|:13
- 3 - A 22 DFFE + 1 3 1 0 |sinlup:U_sinlup|:15
- 8 - A 22 DFFE + 1 3 1 0 |sinlup:U_sinlup|:17
- 2 - A 22 DFFE + 1 3 1 0 |sinlup:U_sinlup|:19
- 2 - A 24 DFFE + 1 3 1 0 |sinlup:U_sinlup|:21
- 8 - A 24 DFFE + 1 3 1 0 |sinlup:U_sinlup|:23
- 3 - A 24 DFFE + 1 1 1 0 |sinlup:U_sinlup|:25
- 4 - A 04 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd5 (|sinlup:U_sinlup|:27)
- 1 - A 03 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd4 (|sinlup:U_sinlup|:28)
- 6 - A 03 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd3 (|sinlup:U_sinlup|:29)
- 3 - A 04 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd2 (|sinlup:U_sinlup|:30)
- 1 - A 14 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd1 (|sinlup:U_sinlup|:31)
- 2 - A 04 DFFE + 1 2 0 7 |sinlup:U_sinlup|phaseadd0 (|sinlup:U_sinlup|:32)
- 1 - A 08 DFFE + 1 1 0 1 |sinlup:U_sinlup|modphase_msb1_ff (|sinlup:U_sinlup|:40)
- 3 - A 08 DFFE + 1 1 0 1 |sinlup:U_sinlup|modphase_msb2_ff (|sinlup:U_sinlup|:41)
- 2 - A 23 DFFE + 1 1 0 1 |sinlup:U_sinlup|qwavesin_ff6 (|sinlup:U_sinlup|:42)
- 1 - A 13 DFFE + 1 1 0 2 |sinlup:U_sinlup|qwavesin_ff5 (|sinlup:U_sinlup|:43)
- 1 - A 16 DFFE + 1 1 0 3 |sinlup:U_sinlup|qwavesin_ff4 (|sinlup:U_sinlup|:44)
- 1 - A 22 DFFE + 1 1 0 4 |sinlup:U_sinlup|qwavesin_ff3 (|sinlup:U_sinlup|:45)
- 7 - A 24 DFFE + 1 1 0 2 |sinlup:U_sinlup|qwavesin_ff2 (|sinlup:U_sinlup|:46)
- 5 - A 24 DFFE + 1 1 0 3 |sinlup:U_sinlup|qwavesin_ff1 (|sinlup:U_sinlup|:47)
- 4 - A 24 DFFE + 1 1 0 4 |sinlup:U_sinlup|qwavesin_ff0 (|sinlup:U_sinlup|:48)
- 2 - A 08 DFFE + 1 1 0 7 |sinlup:U_sinlup|modphase_msb3_ff (|sinlup:U_sinlup|:49)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/ 96( 18%) 27/ 48( 56%) 20/ 48( 41%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 9/ 96( 9%) 0/ 48( 0%) 20/ 48( 41%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 8/ 48( 16%) 7/16( 43%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 123 SYSCLK
Device-Specific Information: f:\dds2\dds\nco.rpt
nco
** EQUATIONS **
FREQWORD0 : INPUT;
FREQWORD1 : INPUT;
FREQWORD2 : INPUT;
FREQWORD3 : INPUT;
FREQWORD4 : INPUT;
FREQWORD5 : INPUT;
FREQWORD6 : INPUT;
FREQWORD7 : INPUT;
FREQWORD8 : INPUT;
FREQWORD9 : INPUT;
FREQWORD10 : INPUT;
FREQWORD11 : INPUT;
FREQWORD12 : INPUT;
FREQWORD13 : INPUT;
FREQWORD14 : INPUT;
FREQWORD15 : INPUT;
FREQWORD16 : INPUT;
FREQWORD17 : INPUT;
FREQWORD18 : INPUT;
FREQWORD19 : INPUT;
FREQWORD20 : INPUT;
FREQWORD21 : INPUT;
FREQWORD22 : INPUT;
FREQWORD23 : INPUT;
FREQWORD24 : INPUT;
FREQWORD25 : INPUT;
FREQWORD26 : INPUT;
FREQWORD27 : INPUT;
FREQWORD28 : INPUT;
FREQWORD29 : INPUT;
FREQWORD30 : INPUT;
FREQWORD31 : INPUT;
FWWRN : INPUT;
PHASEWORD0 : INPUT;
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