phasemod.rpt

利用FPGA实现的DDS

Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                          f:\dds2\dds\phasemod.rpt
phasemod

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        9         SYSCLK


Device-Specific Information:                          f:\dds2\dds\phasemod.rpt
phasemod

** EQUATIONS **

PHASE0   : INPUT;
PHASE1   : INPUT;
PHASE2   : INPUT;
PHASE3   : INPUT;
PHASE4   : INPUT;
PHASE5   : INPUT;
PHASE6   : INPUT;
PHASE7   : INPUT;
RESETN   : INPUT;
SYNCPHSWD0 : INPUT;
SYNCPHSWD1 : INPUT;
SYNCPHSWD2 : INPUT;
SYNCPHSWD3 : INPUT;
SYNCPHSWD4 : INPUT;
SYNCPHSWD5 : INPUT;
SYNCPHSWD6 : INPUT;
SYNCPHSWD7 : INPUT;
SYSCLK   : INPUT;

-- Node name is 'MCOS' 
-- Equation name is 'MCOS', type is output 
MCOS     = !_LC7_C3;

-- Node name is 'MODPHASE0' 
-- Equation name is 'MODPHASE0', type is output 
MODPHASE0 =  mphsreg0;

-- Node name is 'MODPHASE1' 
-- Equation name is 'MODPHASE1', type is output 
MODPHASE1 =  mphsreg1;

-- Node name is 'MODPHASE2' 
-- Equation name is 'MODPHASE2', type is output 
MODPHASE2 =  mphsreg2;

-- Node name is 'MODPHASE3' 
-- Equation name is 'MODPHASE3', type is output 
MODPHASE3 =  mphsreg3;

-- Node name is 'MODPHASE4' 
-- Equation name is 'MODPHASE4', type is output 
MODPHASE4 =  mphsreg4;

-- Node name is 'MODPHASE5' 
-- Equation name is 'MODPHASE5', type is output 
MODPHASE5 =  mphsreg5;

-- Node name is 'MODPHASE6' 
-- Equation name is 'MODPHASE6', type is output 
MODPHASE6 =  mphsreg6;

-- Node name is 'MODPHASE7' 
-- Equation name is 'MODPHASE7', type is output 
MODPHASE7 =  mphsreg7;

-- Node name is ':46' = 'mphsreg0' 
-- Equation name is 'mphsreg0', location is LC1_B11, type is buried.
mphsreg0 = DFFE( _EQ001, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ001 = !PHASE0 & !RESETN &  SYNCPHSWD0
         #  PHASE0 & !RESETN & !SYNCPHSWD0;

-- Node name is ':45' = 'mphsreg1' 
-- Equation name is 'mphsreg1', location is LC4_B11, type is buried.
mphsreg1 = DFFE( _EQ002, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ002 =  _LC2_B11 &  PHASE1 & !RESETN &  SYNCPHSWD1
         # !_LC2_B11 &  PHASE1 & !RESETN & !SYNCPHSWD1
         # !_LC2_B11 & !PHASE1 & !RESETN &  SYNCPHSWD1
         #  _LC2_B11 & !PHASE1 & !RESETN & !SYNCPHSWD1;

-- Node name is ':44' = 'mphsreg2' 
-- Equation name is 'mphsreg2', location is LC6_B11, type is buried.
mphsreg2 = DFFE( _EQ003, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ003 =  _LC3_B11 &  PHASE2 & !RESETN &  SYNCPHSWD2
         #  _LC3_B11 & !PHASE2 & !RESETN & !SYNCPHSWD2
         # !_LC3_B11 &  PHASE2 & !RESETN & !SYNCPHSWD2
         # !_LC3_B11 & !PHASE2 & !RESETN &  SYNCPHSWD2;

-- Node name is ':43' = 'mphsreg3' 
-- Equation name is 'mphsreg3', location is LC8_B11, type is buried.
mphsreg3 = DFFE( _EQ004, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ004 =  _LC5_B11 &  PHASE3 & !RESETN &  SYNCPHSWD3
         #  _LC5_B11 & !PHASE3 & !RESETN & !SYNCPHSWD3
         # !_LC5_B11 & !PHASE3 & !RESETN &  SYNCPHSWD3
         # !_LC5_B11 &  PHASE3 & !RESETN & !SYNCPHSWD3;

-- Node name is ':42' = 'mphsreg4' 
-- Equation name is 'mphsreg4', location is LC7_A7, type is buried.
mphsreg4 = DFFE( _EQ005, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ005 =  _LC7_B11 &  PHASE4 & !RESETN &  SYNCPHSWD4
         #  _LC7_B11 & !PHASE4 & !RESETN & !SYNCPHSWD4
         # !_LC7_B11 & !PHASE4 & !RESETN &  SYNCPHSWD4
         # !_LC7_B11 &  PHASE4 & !RESETN & !SYNCPHSWD4;

-- Node name is ':41' = 'mphsreg5' 
-- Equation name is 'mphsreg5', location is LC1_C3, type is buried.
mphsreg5 = DFFE( _EQ006, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ006 =  _LC2_C3 &  PHASE5 & !RESETN &  SYNCPHSWD5
         #  _LC2_C3 & !PHASE5 & !RESETN & !SYNCPHSWD5
         # !_LC2_C3 & !PHASE5 & !RESETN &  SYNCPHSWD5
         # !_LC2_C3 &  PHASE5 & !RESETN & !SYNCPHSWD5;

-- Node name is ':40' = 'mphsreg6' 
-- Equation name is 'mphsreg6', location is LC5_C3, type is buried.
mphsreg6 = DFFE( _EQ007, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ007 =  _LC6_C3 &  PHASE6 & !RESETN &  SYNCPHSWD6
         #  _LC6_C3 & !PHASE6 & !RESETN & !SYNCPHSWD6
         # !_LC6_C3 & !PHASE6 & !RESETN &  SYNCPHSWD6
         # !_LC6_C3 &  PHASE6 & !RESETN & !SYNCPHSWD6;

-- Node name is '~39~1' = 'mphsreg7~1' 
-- Equation name is '~39~1', location is LC4_C3, type is buried.
-- synthesized logic cell 
_LC4_C3  = DFFE( _EQ008, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ008 = !_LC8_C3 & !PHASE7 & !RESETN &  SYNCPHSWD7
         # !_LC8_C3 &  PHASE7 & !RESETN & !SYNCPHSWD7
         #  _LC8_C3 &  PHASE7 & !RESETN &  SYNCPHSWD7
         #  _LC8_C3 & !PHASE7 & !RESETN & !SYNCPHSWD7;

-- Node name is ':39' = 'mphsreg7' 
-- Equation name is 'mphsreg7', location is LC3_C3, type is buried.
mphsreg7 = DFFE( _EQ009, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ009 =  _LC8_C3 &  PHASE7 & !RESETN &  SYNCPHSWD7
         #  _LC8_C3 & !PHASE7 & !RESETN & !SYNCPHSWD7
         # !_LC8_C3 & !PHASE7 & !RESETN &  SYNCPHSWD7
         # !_LC8_C3 &  PHASE7 & !RESETN & !SYNCPHSWD7;

-- Node name is 'MSIN' 
-- Equation name is 'MSIN', type is output 
MSIN     = !_LC4_C3;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = LCELL( _EQ010);
  _EQ010 =  PHASE1 &  SYNCPHSWD1
         #  PHASE0 &  PHASE1 &  SYNCPHSWD0
         #  PHASE0 &  SYNCPHSWD0 &  SYNCPHSWD1;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B11', type is buried 
_LC5_B11 = LCELL( _EQ011);
  _EQ011 =  _LC3_B11 &  PHASE2
         #  _LC3_B11 &  SYNCPHSWD2
         #  PHASE2 &  SYNCPHSWD2;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = LCELL( _EQ012);
  _EQ012 =  _LC5_B11 &  SYNCPHSWD3
         #  _LC5_B11 &  PHASE3
         #  PHASE3 &  SYNCPHSWD3;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C3', type is buried 
_LC2_C3  = LCELL( _EQ013);
  _EQ013 =  _LC7_B11 &  SYNCPHSWD4
         #  _LC7_B11 &  PHASE4
         #  PHASE4 &  SYNCPHSWD4;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C3', type is buried 
_LC6_C3  = LCELL( _EQ014);
  _EQ014 =  _LC2_C3 &  SYNCPHSWD5
         #  _LC2_C3 &  PHASE5
         #  PHASE5 &  SYNCPHSWD5;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C3', type is buried 
_LC8_C3  = LCELL( _EQ015);
  _EQ015 =  _LC6_C3 &  SYNCPHSWD6
         #  _LC6_C3 &  PHASE6
         #  PHASE6 &  SYNCPHSWD6;

-- Node name is '|lpm_add_sub:Adder|addcore:adder|:114' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ016);
  _EQ016 =  PHASE0 &  SYNCPHSWD0;

-- Node name is ':263' 
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ017);
  _EQ017 = !mphsreg6 &  mphsreg7
         #  mphsreg6 & !mphsreg7;



Project Information                                   f:\dds2\dds\phasemod.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,139K