sinlup.rpt

利用FPGA实现的DDS

-- Equation name is 'phaseadd4', location is LC3_A9, type is buried.
phaseadd4 = DFFE( _EQ008, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ008 =  MODPHASE4 & !MODPHASE6 & !RESETN
         # !MODPHASE4 &  MODPHASE6 & !RESETN;

-- Node name is ':27' = 'phaseadd5' 
-- Equation name is 'phaseadd5', location is LC6_A9, type is buried.
phaseadd5 = DFFE( _EQ009, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ009 = !MODPHASE5 &  MODPHASE6 & !RESETN
         #  MODPHASE5 & !MODPHASE6 & !RESETN;

-- Node name is ':48' = 'qwavesin_ff0' 
-- Equation name is 'qwavesin_ff0', location is LC1_A15, type is buried.
qwavesin_ff0 = DFFE( _EQ010, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ010 =  _EC2_A & !RESETN;

-- Node name is ':47' = 'qwavesin_ff1' 
-- Equation name is 'qwavesin_ff1', location is LC5_A15, type is buried.
qwavesin_ff1 = DFFE( _EQ011, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ011 =  _EC1_A & !RESETN;

-- Node name is ':46' = 'qwavesin_ff2' 
-- Equation name is 'qwavesin_ff2', location is LC7_A15, type is buried.
qwavesin_ff2 = DFFE( _EQ012, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ012 =  _EC3_A & !RESETN;

-- Node name is ':45' = 'qwavesin_ff3' 
-- Equation name is 'qwavesin_ff3', location is LC1_A4, type is buried.
qwavesin_ff3 = DFFE( _EQ013, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ013 =  _EC5_A & !RESETN;

-- Node name is ':44' = 'qwavesin_ff4' 
-- Equation name is 'qwavesin_ff4', location is LC4_A4, type is buried.
qwavesin_ff4 = DFFE( _EQ014, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ014 =  _EC4_A & !RESETN;

-- Node name is ':43' = 'qwavesin_ff5' 
-- Equation name is 'qwavesin_ff5', location is LC8_A3, type is buried.
qwavesin_ff5 = DFFE( _EQ015, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ015 =  _EC6_A & !RESETN;

-- Node name is ':42' = 'qwavesin_ff6' 
-- Equation name is 'qwavesin_ff6', location is LC8_A9, type is buried.
qwavesin_ff6 = DFFE( _EQ016, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ016 =  _EC7_A & !RESETN;

-- Node name is '|LPM_ADD_SUB:470|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ017);
  _EQ017 = !qwavesin_ff0 & !qwavesin_ff1;

-- Node name is '|LPM_ADD_SUB:470|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = LCELL( _EQ018);
  _EQ018 = !qwavesin_ff0 & !qwavesin_ff1 & !qwavesin_ff2;

-- Node name is '|LPM_ADD_SUB:470|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = LCELL( _EQ019);
  _EQ019 =  _LC2_A15 & !qwavesin_ff3;

-- Node name is '|LPM_ADD_SUB:470|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = LCELL( _EQ020);
  _EQ020 =  _LC2_A15 & !qwavesin_ff3 & !qwavesin_ff4;

-- Node name is '|LPM_ADD_SUB:470|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = LCELL( _EQ021);
  _EQ021 =  _LC2_A15 & !qwavesin_ff3 & !qwavesin_ff4 & !qwavesin_ff5;

-- Node name is ':11' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = DFFE( _EQ022, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ022 =  modphase_msb3_ff & !RESETN;

-- Node name is ':13' 
-- Equation name is '_LC7_A9', type is buried 
_LC7_A9  = DFFE( _EQ023, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ023 =  _LC7_A4 &  qwavesin_ff6 & !RESETN
         # !_LC7_A4 &  modphase_msb3_ff & !qwavesin_ff6 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff6 & !RESETN;

-- Node name is ':15' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = DFFE( _EQ024, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ024 =  _LC5_A4 &  qwavesin_ff5 & !RESETN
         # !_LC5_A4 &  modphase_msb3_ff & !qwavesin_ff5 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff5 & !RESETN;

-- Node name is ':17' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = DFFE( _EQ025, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ025 =  _LC3_A4 &  qwavesin_ff4 & !RESETN
         # !_LC3_A4 &  modphase_msb3_ff & !qwavesin_ff4 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff4 & !RESETN;

-- Node name is ':19' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = DFFE( _EQ026, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ026 =  _LC2_A15 &  qwavesin_ff3 & !RESETN
         # !_LC2_A15 &  modphase_msb3_ff & !qwavesin_ff3 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff3 & !RESETN;

-- Node name is ':21' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = DFFE( _EQ027, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ027 =  _LC6_A15 &  qwavesin_ff2 & !RESETN
         # !_LC6_A15 &  modphase_msb3_ff & !qwavesin_ff2 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff2 & !RESETN;

-- Node name is ':23' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = DFFE( _EQ028, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ028 =  modphase_msb3_ff &  qwavesin_ff0 & !qwavesin_ff1 & !RESETN
         # !qwavesin_ff0 &  qwavesin_ff1 & !RESETN
         # !modphase_msb3_ff &  qwavesin_ff1 & !RESETN;

-- Node name is ':25' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = DFFE( _EQ029, GLOBAL( SYSCLK),  VCC,  VCC,  VCC);
  _EQ029 =  qwavesin_ff0 & !RESETN;

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_A', type is memory 
_EC2_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_A', type is memory 
_EC1_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_A', type is memory 
_EC3_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_A', type is memory 
_EC5_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_A', type is memory 
_EC4_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_A', type is memory 
_EC6_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);

-- Node name is '|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_A', type is memory 
_EC7_A   = MEMORY_SEGMENT( VCC, GLOBAL( SYSCLK), VCC, GND, VCC, phaseadd0, phaseadd1, phaseadd2, phaseadd3, phaseadd4, phaseadd5, VCC, VCC, VCC, VCC, VCC,);



Project Information                                     f:\dds2\dds\sinlup.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,836K