📄 sinlup.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dds2\dds\sinlup.rpt
sinlup
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 NCOOUT0
71 - - A -- OUTPUT 0 1 0 0 NCOOUT1
49 - - - 16 OUTPUT 0 1 0 0 NCOOUT2
18 - - A -- OUTPUT 0 1 0 0 NCOOUT3
17 - - A -- OUTPUT 0 1 0 0 NCOOUT4
8 - - - 03 OUTPUT 0 1 0 0 NCOOUT5
19 - - A -- OUTPUT 0 1 0 0 NCOOUT6
16 - - A -- OUTPUT 0 1 0 0 NCOOUT7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\dds2\dds\sinlup.rpt
sinlup
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 15 AND2 0 2 0 1 |LPM_ADD_SUB:470|addcore:adder|:121
- 2 - A 15 AND2 0 3 0 4 |LPM_ADD_SUB:470|addcore:adder|:125
- 3 - A 04 AND2 0 2 0 1 |LPM_ADD_SUB:470|addcore:adder|:129
- 5 - A 04 AND2 0 3 0 1 |LPM_ADD_SUB:470|addcore:adder|:133
- 7 - A 04 AND2 0 4 0 1 |LPM_ADD_SUB:470|addcore:adder|:137
- - 2 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_0
- - 1 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_1
- - 3 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_2
- - 5 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_3
- - 4 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_4
- - 6 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_5
- - 7 A -- MEM_SGMT 0 6 0 1 |romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|segment0_6
- 1 - A 03 DFFE + 1 1 1 0 :11
- 7 - A 09 DFFE + 1 3 1 0 :13
- 6 - A 04 DFFE + 1 3 1 0 :15
- 2 - A 04 DFFE + 1 3 1 0 :17
- 8 - A 04 DFFE + 1 3 1 0 :19
- 3 - A 15 DFFE + 1 3 1 0 :21
- 4 - A 15 DFFE + 1 3 1 0 :23
- 8 - A 15 DFFE + 1 1 1 0 :25
- 6 - A 09 DFFE + 3 0 0 7 phaseadd5 (:27)
- 3 - A 09 DFFE + 3 0 0 7 phaseadd4 (:28)
- 4 - A 09 DFFE + 3 0 0 7 phaseadd3 (:29)
- 1 - A 09 DFFE + 3 0 0 7 phaseadd2 (:30)
- 2 - A 09 DFFE + 3 0 0 7 phaseadd1 (:31)
- 5 - A 09 DFFE + 3 0 0 7 phaseadd0 (:32)
- 3 - A 03 DFFE + 2 0 0 1 modphase_msb1_ff (:40)
- 4 - A 03 DFFE + 1 1 0 1 modphase_msb2_ff (:41)
- 8 - A 09 DFFE + 1 1 0 1 qwavesin_ff6 (:42)
- 8 - A 03 DFFE + 1 1 0 2 qwavesin_ff5 (:43)
- 4 - A 04 DFFE + 1 1 0 3 qwavesin_ff4 (:44)
- 1 - A 04 DFFE + 1 1 0 4 qwavesin_ff3 (:45)
- 7 - A 15 DFFE + 1 1 0 2 qwavesin_ff2 (:46)
- 5 - A 15 DFFE + 1 1 0 3 qwavesin_ff1 (:47)
- 1 - A 15 DFFE + 1 1 0 4 qwavesin_ff0 (:48)
- 2 - A 03 DFFE + 1 1 0 7 modphase_msb3_ff (:49)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\dds2\dds\sinlup.rpt
sinlup
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 12/ 48( 25%) 2/ 48( 4%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\dds2\dds\sinlup.rpt
sinlup
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 SYSCLK
Device-Specific Information: f:\dds2\dds\sinlup.rpt
sinlup
** EQUATIONS **
MODPHASE0 : INPUT;
MODPHASE1 : INPUT;
MODPHASE2 : INPUT;
MODPHASE3 : INPUT;
MODPHASE4 : INPUT;
MODPHASE5 : INPUT;
MODPHASE6 : INPUT;
MODPHASE7 : INPUT;
RESETN : INPUT;
SYSCLK : INPUT;
-- Node name is ':40' = 'modphase_msb1_ff'
-- Equation name is 'modphase_msb1_ff', location is LC3_A3, type is buried.
modphase_msb1_ff = DFFE( _EQ001, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ001 = MODPHASE7 & !RESETN;
-- Node name is ':41' = 'modphase_msb2_ff'
-- Equation name is 'modphase_msb2_ff', location is LC4_A3, type is buried.
modphase_msb2_ff = DFFE( _EQ002, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ002 = modphase_msb1_ff & !RESETN;
-- Node name is ':49' = 'modphase_msb3_ff'
-- Equation name is 'modphase_msb3_ff', location is LC2_A3, type is buried.
modphase_msb3_ff = DFFE( _EQ003, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ003 = modphase_msb3_ff & RESETN
# modphase_msb2_ff & !RESETN;
-- Node name is 'NCOOUT0'
-- Equation name is 'NCOOUT0', type is output
NCOOUT0 = _LC8_A15;
-- Node name is 'NCOOUT1'
-- Equation name is 'NCOOUT1', type is output
NCOOUT1 = _LC4_A15;
-- Node name is 'NCOOUT2'
-- Equation name is 'NCOOUT2', type is output
NCOOUT2 = _LC3_A15;
-- Node name is 'NCOOUT3'
-- Equation name is 'NCOOUT3', type is output
NCOOUT3 = _LC8_A4;
-- Node name is 'NCOOUT4'
-- Equation name is 'NCOOUT4', type is output
NCOOUT4 = _LC2_A4;
-- Node name is 'NCOOUT5'
-- Equation name is 'NCOOUT5', type is output
NCOOUT5 = _LC6_A4;
-- Node name is 'NCOOUT6'
-- Equation name is 'NCOOUT6', type is output
NCOOUT6 = _LC7_A9;
-- Node name is 'NCOOUT7'
-- Equation name is 'NCOOUT7', type is output
NCOOUT7 = _LC1_A3;
-- Node name is ':32' = 'phaseadd0'
-- Equation name is 'phaseadd0', location is LC5_A9, type is buried.
phaseadd0 = DFFE( _EQ004, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ004 = MODPHASE0 & !MODPHASE6 & !RESETN
# !MODPHASE0 & MODPHASE6 & !RESETN;
-- Node name is ':31' = 'phaseadd1'
-- Equation name is 'phaseadd1', location is LC2_A9, type is buried.
phaseadd1 = DFFE( _EQ005, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ005 = MODPHASE1 & !MODPHASE6 & !RESETN
# !MODPHASE1 & MODPHASE6 & !RESETN;
-- Node name is ':30' = 'phaseadd2'
-- Equation name is 'phaseadd2', location is LC1_A9, type is buried.
phaseadd2 = DFFE( _EQ006, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ006 = MODPHASE2 & !MODPHASE6 & !RESETN
# !MODPHASE2 & MODPHASE6 & !RESETN;
-- Node name is ':29' = 'phaseadd3'
-- Equation name is 'phaseadd3', location is LC4_A9, type is buried.
phaseadd3 = DFFE( _EQ007, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ007 = MODPHASE3 & !MODPHASE6 & !RESETN
# !MODPHASE3 & MODPHASE6 & !RESETN;
-- Node name is ':28' = 'phaseadd4'
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