loadfw.vhd

利用FPGA实现的DDS

 -----------------------------------------------------------------------------                                                                     
 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                        
 -- Description          :                                                                                                                                  
 -- This module will load the frequency word into the phase accumulator
 -- synchronously at the proper pipeline timing.  The input to this module
 -- will be the frequency word and load write strobe.  The output will be
 -- the synchronous frequency word.
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY loadfw IS
    PORT(
         SYSCLK    : IN  STD_LOGIC;                      -- system clock input
         RESETN    : IN  STD_LOGIC; 			         -- global reset
         FWWRN     : IN  STD_LOGIC; 			         -- low asserted frequency word write strobe
         FREQWORD  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0); -- input frequency word from external pins
         SYNCFREQ  : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)  -- synchronous frequency word
        );
END loadfw;

ARCHITECTURE Load OF loadfw IS
    SIGNAL fwreg    : STD_LOGIC_VECTOR (31 DOWNTO 0);--  input frequency word registered
    SIGNAL fwwrnm   : STD_LOGIC;                    --  meta-stable frequency word write strobe 
    SIGNAL fwwrns   : STD_LOGIC ;                   --  synchronous frequency word write strobe
    SIGNAL loadp1, loadp2, loadp3, loadp4     : STD_LOGIC;                     --  synchronous load strobes 
    SIGNAL pipefw1, pipefw2, pipefw3, pipefw4 : STD_LOGIC_VECTOR (7 DOWNTO 0); --  pipelined FW registered values

BEGIN
    SYNCFREQ <= pipefw4 & pipefw3 & pipefw2 & pipefw1;
-- register the input phase word
Reginphaword:process(FWWRN,RESETN)
    begin
	  if RESETN='1' then
			fwreg  <=(others=>'0');
      else
            fwreg <= FREQWORD;
      end if; 
end process;

-- get a synchronous load strobe on the rising edge of PWWRN	 
Getstrobe:process(SYSCLK,RESETN)
    begin
      if SYSCLK'event and SYSCLK='1' then
	     if RESETN='1' then
		    fwwrnm  <= '1';
		    fwwrns  <= '1';
		    loadp1  <= '0';
		    loadp2  <= '0';
		    loadp3  <= '0';
		    loadp4  <= '0';
            pipefw1 <=(others=>'0');
            pipefw2 <=(others=>'0');
            pipefw3 <=(others=>'0');
            pipefw4 <=(others=>'0');
         else 
            fwwrnm <= FWWRN;
            fwwrns <= fwwrnm;	              -- got a synchronous FWWRN
            loadp1  <= (NOT fwwrns) AND fwwrnm;-- 微分电路
            loadp2 <= loadp1;
		    loadp3 <= loadp2;
		    loadp4 <= loadp3;

               if loadp1 ='1' then              -- got rising edge		      
                   pipefw1 <= fwreg(7 DOWNTO 0);	          
		       else
			       pipefw1 <= pipefw1; end if;
		       if loadp2 ='1' then
			       pipefw2 <= fwreg(15 DOWNTO 8);
		       else
			       pipefw2 <= pipefw2; end if;
		       if loadp3 ='1' then
			       pipefw3 <= fwreg(23 DOWNTO 16);
		       else
			       pipefw3 <= pipefw3; end if;
		       if loadp4 ='1' then
			       pipefw4 <= fwreg(31 DOWNTO 24);
		       else
			       pipefw4 <= pipefw4; end if;
          end if;
      end if; 
end process;

END Load;