phasemod.vhd

利用FPGA实现的DDS

 -----------------------------------------------------------------------------                                                                     
 -- Project Name         : NCO                                            
 --                                                                             
 -- Author               : Bluetea
 -- Creation Date        : 03/11/04 18:20:21                                              
 -- Version Number       : 1.0                                                                                                                                                                        
 -- Description          :                                                                                                                                  
 -- This module will take the phase value from the phase accumulator and
 -- modulate it with the synchronous version of the modulation phase word.
 -----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY phasemod IS
    PORT(
         SYSCLK    : IN  STD_LOGIC;                     -- system clock input
         RESETN    : IN  STD_LOGIC; 			        -- global reset
         SYNCPHSWD : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); -- synchronous phase word
         PHASE     : IN  STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit quantized phase value
         MCOS      : OUT STD_LOGIC;                     -- modulated digital cos output
         MSIN      : OUT STD_LOGIC;                     -- modulated digital sin output
         MODPHASE  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)  -- modulated phase output
        );
END phasemod;

ARCHITECTURE Phmodul OF phasemod IS
    SIGNAL mphs	    : STD_LOGIC_VECTOR (7 DOWNTO 0);--  modulated phase from adder
    SIGNAL mphsreg	: STD_LOGIC_VECTOR (7 DOWNTO 0);--  modulated phase registered
    SIGNAL gnd	    : STD_LOGIC;                    --  ground 
    SIGNAL c	    : STD_LOGIC ;                   --  carry from adder not used

    COMPONENT lpm_add_sub
	GENERIC (
		LPM_WIDTH	          : POSITIVE;
		LPM_DIRECTION         : STRING;
		ONE_INPUT_IS_CONSTANT : STRING
	);
	PORT (
		dataa,datab	 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		overflow     : OUT STD_LOGIC ;
		cin	         : IN STD_LOGIC ;
		result	     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;
BEGIN
	Adder : lpm_add_sub
	GENERIC MAP (LPM_WIDTH=>8,LPM_DIRECTION=>"ADD",ONE_INPUT_IS_CONSTANT=>"NO")
	PORT MAP (dataa=>PHASE,datab=>SYNCPHSWD,cin=>gnd,overflow=>c,result=>mphs);
	
       gnd <= '0';
       MODPHASE <= mphsreg;
	   MSIN     <= not mphsreg(7);
	   MCOS     <= not (mphsreg(7) xor mphsreg(6));

    process(SYSCLK,RESETN)
    begin
	  if SYSCLK'event and SYSCLK='1' then
		 if RESETN='1' then
			mphsreg <=(others=>'0');
         else
            mphsreg <= mphs;
         end if;
      end if; 
	end process;

END Phmodul;