ps2.tan.qmsg

FPGA的PS2口接口程序

{ "Info" "ITDB_TH_RESULT" "data_scanC:inst\|now_kbclk kb_clk clk -4.578 ns register " "Info: th for register \"data_scanC:inst\|now_kbclk\" (data pin = \"kb_clk\", clock pin = \"clk\") is -4.578 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 2.772 ns data_scanC:inst\|now_kbclk 3 REG LCFF_X22_Y6_N13 5 " "Info: 3: + IC(0.823 ns) + CELL(0.666 ns) = 2.772 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 5; REG Node = 'data_scanC:inst\|now_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.15 % ) " "Info: Total cell delay = 1.806 ns ( 65.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.966 ns ( 34.85 % ) " "Info: Total interconnect delay = 0.966 ns ( 34.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.656 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns kb_clk 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'kb_clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { kb_clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 96 -144 24 112 "kb_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.232 ns) + CELL(0.460 ns) 7.656 ns data_scanC:inst\|now_kbclk 2 REG LCFF_X22_Y6_N13 5 " "Info: 2: + IC(6.232 ns) + CELL(0.460 ns) = 7.656 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 5; REG Node = 'data_scanC:inst\|now_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.692 ns" { kb_clk data_scanC:inst|now_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 18.60 % ) " "Info: Total cell delay = 1.424 ns ( 18.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.232 ns ( 81.40 % ) " "Info: Total interconnect delay = 6.232 ns ( 81.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.656 ns" { kb_clk data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.656 ns" { kb_clk {} kb_clk~combout {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 6.232ns } { 0.000ns 0.964ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.656 ns" { kb_clk data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.656 ns" { kb_clk {} kb_clk~combout {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 6.232ns } { 0.000ns 0.964ns 0.460ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 20:34:20 2009 " "Info: Processing ended: Thu Jan 08 20:34:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}