📄 ps2.tan.qmsg

📁 FPGA的PS2口接口程序
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "data_scanC:inst\|pre_kbclk reset clk 5.872 ns register " "Info: tsu for register \"data_scanC:inst\|pre_kbclk\" (data pin = \"reset\", clock pin = \"clk\") is 5.872 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.684 ns + Longest pin register " "Info: + Longest pin to register delay is 8.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_56 40 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 40; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 168 -112 56 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.845 ns) + CELL(0.855 ns) 8.684 ns data_scanC:inst\|pre_kbclk 2 REG LCFF_X22_Y6_N15 4 " "Info: 2: + IC(6.845 ns) + CELL(0.855 ns) = 8.684 ns; Loc. = LCFF_X22_Y6_N15; Fanout = 4; REG Node = 'data_scanC:inst\|pre_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { reset data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.839 ns ( 21.18 % ) " "Info: Total cell delay = 1.839 ns ( 21.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.845 ns ( 78.82 % ) " "Info: Total interconnect delay = 6.845 ns ( 78.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.684 ns" { reset data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.684 ns" { reset {} reset~combout {} data_scanC:inst|pre_kbclk {} } { 0.000ns 0.000ns 6.845ns } { 0.000ns 0.984ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 2.772 ns data_scanC:inst\|pre_kbclk 3 REG LCFF_X22_Y6_N15 4 " "Info: 3: + IC(0.823 ns) + CELL(0.666 ns) = 2.772 ns; Loc. = LCFF_X22_Y6_N15; Fanout = 4; REG Node = 'data_scanC:inst\|pre_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.15 % ) " "Info: Total cell delay = 1.806 ns ( 65.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.966 ns ( 34.85 % ) " "Info: Total interconnect delay = 0.966 ns ( 34.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|pre_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.684 ns" { reset data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.684 ns" { reset {} reset~combout {} data_scanC:inst|pre_kbclk {} } { 0.000ns 0.000ns 6.845ns } { 0.000ns 0.984ns 0.855ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|pre_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|pre_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[6\] convert:inst7\|shifted 24.910 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[6\]\" through register \"convert:inst7\|shifted\" is 24.910 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.040 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.481 ns) + CELL(0.970 ns) 3.591 ns convert:inst7\|prepared_r 2 REG LCFF_X20_Y6_N9 2 " "Info: 2: + IC(1.481 ns) + CELL(0.970 ns) = 3.591 ns; Loc. = LCFF_X20_Y6_N9; Fanout = 2; REG Node = 'convert:inst7\|prepared_r'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.451 ns" { clk convert:inst7|prepared_r } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.953 ns) + CELL(0.000 ns) 5.544 ns convert:inst7\|prepared_r~clkctrl 3 COMB CLKCTRL_G5 3 " "Info: 3: + IC(1.953 ns) + CELL(0.000 ns) = 5.544 ns; Loc. = CLKCTRL_G5; Fanout = 3; COMB Node = 'convert:inst7\|prepared_r~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.953 ns" { convert:inst7|prepared_r convert:inst7|prepared_r~clkctrl } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 7.040 ns convert:inst7\|shifted 4 REG LCFF_X21_Y7_N17 23 " "Info: 4: + IC(0.830 ns) + CELL(0.666 ns) = 7.040 ns; Loc. = LCFF_X21_Y7_N17; Fanout = 23; REG Node = 'convert:inst7\|shifted'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { convert:inst7|prepared_r~clkctrl convert:inst7|shifted } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.43 % ) " "Info: Total cell delay = 2.776 ns ( 39.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.264 ns ( 60.57 % ) " "Info: Total interconnect delay = 4.264 ns ( 60.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.040 ns" { clk convert:inst7|prepared_r convert:inst7|prepared_r~clkctrl convert:inst7|shifted } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.040 ns" { clk {} clk~combout {} convert:inst7|prepared_r {} convert:inst7|prepared_r~clkctrl {} convert:inst7|shifted {} } { 0.000ns 0.000ns 1.481ns 1.953ns 0.830ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.566 ns + Longest register pin " "Info: + Longest register to pin delay is 17.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns convert:inst7\|shifted 1 REG LCFF_X21_Y7_N17 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y7_N17; Fanout = 23; REG Node = 'convert:inst7\|shifted'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { convert:inst7|shifted } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.556 ns) + CELL(0.206 ns) 1.762 ns convert:inst7\|Selector1~5446 2 COMB LCCOMB_X18_Y9_N10 3 " "Info: 2: + IC(1.556 ns) + CELL(0.206 ns) = 1.762 ns; Loc. = LCCOMB_X18_Y9_N10; Fanout = 3; COMB Node = 'convert:inst7\|Selector1~5446'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { convert:inst7|shifted convert:inst7|Selector1~5446 } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.370 ns) 3.244 ns convert:inst7\|Selector4~1920 3 COMB LCCOMB_X18_Y7_N0 1 " "Info: 3: + IC(1.112 ns) + CELL(0.370 ns) = 3.244 ns; Loc. = LCCOMB_X18_Y7_N0; Fanout = 1; COMB Node = 'convert:inst7\|Selector4~1920'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.482 ns" { convert:inst7|Selector1~5446 convert:inst7|Selector4~1920 } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.657 ns) + CELL(0.206 ns) 4.107 ns convert:inst7\|Selector4~1921 4 COMB LCCOMB_X18_Y8_N24 1 " "Info: 4: + IC(0.657 ns) + CELL(0.206 ns) = 4.107 ns; Loc. = LCCOMB_X18_Y8_N24; Fanout = 1; COMB Node = 'convert:inst7\|Selector4~1921'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.863 ns" { convert:inst7|Selector4~1920 convert:inst7|Selector4~1921 } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(0.206 ns) 4.976 ns convert:inst7\|Selector4~1927 5 COMB LCCOMB_X18_Y8_N20 3 " "Info: 5: + IC(0.663 ns) + CELL(0.206 ns) = 4.976 ns; Loc. = LCCOMB_X18_Y8_N20; Fanout = 3; COMB Node = 'convert:inst7\|Selector4~1927'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { convert:inst7|Selector4~1921 convert:inst7|Selector4~1927 } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.893 ns) + CELL(0.650 ns) 7.519 ns convert:inst7\|LessThan1~118 6 COMB LCCOMB_X21_Y6_N26 1 " "Info: 6: + IC(1.893 ns) + CELL(0.650 ns) = 7.519 ns; Loc. = LCCOMB_X21_Y6_N26; Fanout = 1; COMB Node = 'convert:inst7\|LessThan1~118'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.543 ns" { convert:inst7|Selector4~1927 convert:inst7|LessThan1~118 } "NODE_NAME" } } { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 126 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.616 ns) 8.506 ns segmain:inst8\|Mux2~358 7 COMB LCCOMB_X21_Y6_N30 1 " "Info: 7: + IC(0.371 ns) + CELL(0.616 ns) = 8.506 ns; Loc. = LCCOMB_X21_Y6_N30; Fanout = 1; COMB Node = 'segmain:inst8\|Mux2~358'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.987 ns" { convert:inst7|LessThan1~118 segmain:inst8|Mux2~358 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.624 ns) 9.501 ns segmain:inst8\|Mux2~360 8 COMB LCCOMB_X21_Y6_N8 1 " "Info: 8: + IC(0.371 ns) + CELL(0.624 ns) = 9.501 ns; Loc. = LCCOMB_X21_Y6_N8; Fanout = 1; COMB Node = 'segmain:inst8\|Mux2~360'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.995 ns" { segmain:inst8|Mux2~358 segmain:inst8|Mux2~360 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.471 ns) + CELL(0.651 ns) 11.623 ns segmain:inst8\|Mux2 9 COMB LCCOMB_X22_Y7_N2 7 " "Info: 9: + IC(1.471 ns) + CELL(0.651 ns) = 11.623 ns; Loc. = LCCOMB_X22_Y7_N2; Fanout = 7; COMB Node = 'segmain:inst8\|Mux2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.122 ns" { segmain:inst8|Mux2~360 segmain:inst8|Mux2 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.624 ns) 12.649 ns segmain:inst8\|WideOr0~15 10 COMB LCCOMB_X22_Y7_N30 1 " "Info: 10: + IC(0.402 ns) + CELL(0.624 ns) = 12.649 ns; Loc. = LCCOMB_X22_Y7_N30; Fanout = 1; COMB Node = 'segmain:inst8\|WideOr0~15'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.026 ns" { segmain:inst8|Mux2 segmain:inst8|WideOr0~15 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.811 ns) + CELL(3.106 ns) 17.566 ns 78leddata\[6\] 11 PIN PIN_115 0 " "Info: 11: + IC(1.811 ns) + CELL(3.106 ns) = 17.566 ns; Loc. = PIN_115; Fanout = 0; PIN Node = '78leddata\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.917 ns" { segmain:inst8|WideOr0~15 78leddata[6] } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 336 512 256 "78leddata\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.259 ns ( 41.32 % ) " "Info: Total cell delay = 7.259 ns ( 41.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.307 ns ( 58.68 % ) " "Info: Total interconnect delay = 10.307 ns ( 58.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.566 ns" { convert:inst7|shifted convert:inst7|Selector1~5446 convert:inst7|Selector4~1920 convert:inst7|Selector4~1921 convert:inst7|Selector4~1927 convert:inst7|LessThan1~118 segmain:inst8|Mux2~358 segmain:inst8|Mux2~360 segmain:inst8|Mux2 segmain:inst8|WideOr0~15 78leddata[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.566 ns" { convert:inst7|shifted {} convert:inst7|Selector1~5446 {} convert:inst7|Selector4~1920 {} convert:inst7|Selector4~1921 {} convert:inst7|Selector4~1927 {} convert:inst7|LessThan1~118 {} segmain:inst8|Mux2~358 {} segmain:inst8|Mux2~360 {} segmain:inst8|Mux2 {} segmain:inst8|WideOr0~15 {} 78leddata[6] {} } { 0.000ns 1.556ns 1.112ns 0.657ns 0.663ns 1.893ns 0.371ns 0.371ns 1.471ns 0.402ns 1.811ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.206ns 0.650ns 0.616ns 0.624ns 0.651ns 0.624ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.040 ns" { clk convert:inst7|prepared_r convert:inst7|prepared_r~clkctrl convert:inst7|shifted } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.040 ns" { clk {} clk~combout {} convert:inst7|prepared_r {} convert:inst7|prepared_r~clkctrl {} convert:inst7|shifted {} } { 0.000ns 0.000ns 1.481ns 1.953ns 0.830ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.566 ns" { convert:inst7|shifted convert:inst7|Selector1~5446 convert:inst7|Selector4~1920 convert:inst7|Selector4~1921 convert:inst7|Selector4~1927 convert:inst7|LessThan1~118 segmain:inst8|Mux2~358 segmain:inst8|Mux2~360 segmain:inst8|Mux2 segmain:inst8|WideOr0~15 78leddata[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.566 ns" { convert:inst7|shifted {} convert:inst7|Selector1~5446 {} convert:inst7|Selector4~1920 {} convert:inst7|Selector4~1921 {} convert:inst7|Selector4~1927 {} convert:inst7|LessThan1~118 {} segmain:inst8|Mux2~358 {} segmain:inst8|Mux2~360 {} segmain:inst8|Mux2 {} segmain:inst8|WideOr0~15 {} 78leddata[6] {} } { 0.000ns 1.556ns 1.112ns 0.657ns 0.663ns 1.893ns 0.371ns 0.371ns 1.471ns 0.402ns 1.811ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.206ns 0.650ns 0.616ns 0.624ns 0.651ns 0.624ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset 78leddata\[6\] 20.129 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"78leddata\[6\]\" is 20.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_56 40 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 40; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 168 -112 56 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.965 ns) + CELL(0.624 ns) 8.573 ns segmain:inst8\|Mux2~356 2 COMB LCCOMB_X21_Y6_N10 2 " "Info: 2: + IC(6.965 ns) + CELL(0.624 ns) = 8.573 ns; Loc. = LCCOMB_X21_Y6_N10; Fanout = 2; COMB Node = 'segmain:inst8\|Mux2~356'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.589 ns" { reset segmain:inst8|Mux2~356 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.366 ns) 10.023 ns segmain:inst8\|Mux1~33 3 COMB LCCOMB_X21_Y7_N18 2 " "Info: 3: + IC(1.084 ns) + CELL(0.366 ns) = 10.023 ns; Loc. = LCCOMB_X21_Y7_N18; Fanout = 2; COMB Node = 'segmain:inst8\|Mux1~33'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.450 ns" { segmain:inst8|Mux2~356 segmain:inst8|Mux1~33 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 10.603 ns segmain:inst8\|Mux2~359 4 COMB LCCOMB_X21_Y7_N28 1 " "Info: 4: + IC(0.374 ns) + CELL(0.206 ns) = 10.603 ns; Loc. = LCCOMB_X21_Y7_N28; Fanout = 1; COMB Node = 'segmain:inst8\|Mux2~359'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { segmain:inst8|Mux1~33 segmain:inst8|Mux2~359 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.366 ns) 12.064 ns segmain:inst8\|Mux2~360 5 COMB LCCOMB_X21_Y6_N8 1 " "Info: 5: + IC(1.095 ns) + CELL(0.366 ns) = 12.064 ns; Loc. = LCCOMB_X21_Y6_N8; Fanout = 1; COMB Node = 'segmain:inst8\|Mux2~360'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { segmain:inst8|Mux2~359 segmain:inst8|Mux2~360 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.471 ns) + CELL(0.651 ns) 14.186 ns segmain:inst8\|Mux2 6 COMB LCCOMB_X22_Y7_N2 7 " "Info: 6: + IC(1.471 ns) + CELL(0.651 ns) = 14.186 ns; Loc. = LCCOMB_X22_Y7_N2; Fanout = 7; COMB Node = 'segmain:inst8\|Mux2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.122 ns" { segmain:inst8|Mux2~360 segmain:inst8|Mux2 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.624 ns) 15.212 ns segmain:inst8\|WideOr0~15 7 COMB LCCOMB_X22_Y7_N30 1 " "Info: 7: + IC(0.402 ns) + CELL(0.624 ns) = 15.212 ns; Loc. = LCCOMB_X22_Y7_N30; Fanout = 1; COMB Node = 'segmain:inst8\|WideOr0~15'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.026 ns" { segmain:inst8|Mux2 segmain:inst8|WideOr0~15 } "NODE_NAME" } } { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.811 ns) + CELL(3.106 ns) 20.129 ns 78leddata\[6\] 8 PIN PIN_115 0 " "Info: 8: + IC(1.811 ns) + CELL(3.106 ns) = 20.129 ns; Loc. = PIN_115; Fanout = 0; PIN Node = '78leddata\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.917 ns" { segmain:inst8|WideOr0~15 78leddata[6] } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 336 512 256 "78leddata\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.927 ns ( 34.41 % ) " "Info: Total cell delay = 6.927 ns ( 34.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.202 ns ( 65.59 % ) " "Info: Total interconnect delay = 13.202 ns ( 65.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.129 ns" { reset segmain:inst8|Mux2~356 segmain:inst8|Mux1~33 segmain:inst8|Mux2~359 segmain:inst8|Mux2~360 segmain:inst8|Mux2 segmain:inst8|WideOr0~15 78leddata[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.129 ns" { reset {} reset~combout {} segmain:inst8|Mux2~356 {} segmain:inst8|Mux1~33 {} segmain:inst8|Mux2~359 {} segmain:inst8|Mux2~360 {} segmain:inst8|Mux2 {} segmain:inst8|WideOr0~15 {} 78leddata[6] {} } { 0.000ns 0.000ns 6.965ns 1.084ns 0.374ns 1.095ns 1.471ns 0.402ns 1.811ns } { 0.000ns 0.984ns 0.624ns 0.366ns 0.206ns 0.366ns 0.651ns 0.624ns 3.106ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
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