ps2.tan.qmsg

FPGA的PS2口接口程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "convert:inst7\|prepared_r " "Info: Detected ripple clock \"convert:inst7\|prepared_r\" as buffer" {  } { { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 28 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "convert:inst7\|prepared_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register data_scanC:inst\|now_kbclk register data_scanC:inst\|tmp\[3\] 236.85 MHz 4.222 ns Internal " "Info: Clock \"clk\" has Internal fmax of 236.85 MHz between source register \"data_scanC:inst\|now_kbclk\" and destination register \"data_scanC:inst\|tmp\[3\]\" (period= 4.222 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.958 ns + Longest register register " "Info: + Longest register to register delay is 3.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_scanC:inst\|now_kbclk 1 REG LCFF_X22_Y6_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 5; REG Node = 'data_scanC:inst\|now_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_scanC:inst|now_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.936 ns) + CELL(0.606 ns) 2.542 ns data_scanC:inst\|Decoder0~217 2 COMB LCCOMB_X22_Y6_N4 2 " "Info: 2: + IC(1.936 ns) + CELL(0.606 ns) = 2.542 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 2; COMB Node = 'data_scanC:inst\|Decoder0~217'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { data_scanC:inst|now_kbclk data_scanC:inst|Decoder0~217 } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.624 ns) 3.850 ns data_scanC:inst\|tmp\[3\]~811 3 COMB LCCOMB_X22_Y6_N20 1 " "Info: 3: + IC(0.684 ns) + CELL(0.624 ns) = 3.850 ns; Loc. = LCCOMB_X22_Y6_N20; Fanout = 1; COMB Node = 'data_scanC:inst\|tmp\[3\]~811'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.308 ns" { data_scanC:inst|Decoder0~217 data_scanC:inst|tmp[3]~811 } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.958 ns data_scanC:inst\|tmp\[3\] 4 REG LCFF_X22_Y6_N21 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.958 ns; Loc. = LCFF_X22_Y6_N21; Fanout = 2; REG Node = 'data_scanC:inst\|tmp\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { data_scanC:inst|tmp[3]~811 data_scanC:inst|tmp[3] } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.338 ns ( 33.80 % ) " "Info: Total cell delay = 1.338 ns ( 33.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.620 ns ( 66.20 % ) " "Info: Total interconnect delay = 2.620 ns ( 66.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.958 ns" { data_scanC:inst|now_kbclk data_scanC:inst|Decoder0~217 data_scanC:inst|tmp[3]~811 data_scanC:inst|tmp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.958 ns" { data_scanC:inst|now_kbclk {} data_scanC:inst|Decoder0~217 {} data_scanC:inst|tmp[3]~811 {} data_scanC:inst|tmp[3] {} } { 0.000ns 1.936ns 0.684ns 0.000ns } { 0.000ns 0.606ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 2.772 ns data_scanC:inst\|tmp\[3\] 3 REG LCFF_X22_Y6_N21 2 " "Info: 3: + IC(0.823 ns) + CELL(0.666 ns) = 2.772 ns; Loc. = LCFF_X22_Y6_N21; Fanout = 2; REG Node = 'data_scanC:inst\|tmp\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl data_scanC:inst|tmp[3] } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.15 % ) " "Info: Total cell delay = 1.806 ns ( 65.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.966 ns ( 34.85 % ) " "Info: Total interconnect delay = 0.966 ns ( 34.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|tmp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|tmp[3] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.772 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 31 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 31; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 -160 8 256 "clk" "" } { 56 344 376 72 "clk" "" } { 56 48 112 72 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 2.772 ns data_scanC:inst\|now_kbclk 3 REG LCFF_X22_Y6_N13 5 " "Info: 3: + IC(0.823 ns) + CELL(0.666 ns) = 2.772 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 5; REG Node = 'data_scanC:inst\|now_kbclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.15 % ) " "Info: Total cell delay = 1.806 ns ( 65.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.966 ns ( 34.85 % ) " "Info: Total interconnect delay = 0.966 ns ( 34.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|tmp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|tmp[3] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.958 ns" { data_scanC:inst|now_kbclk data_scanC:inst|Decoder0~217 data_scanC:inst|tmp[3]~811 data_scanC:inst|tmp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.958 ns" { data_scanC:inst|now_kbclk {} data_scanC:inst|Decoder0~217 {} data_scanC:inst|tmp[3]~811 {} data_scanC:inst|tmp[3] {} } { 0.000ns 1.936ns 0.684ns 0.000ns } { 0.000ns 0.606ns 0.624ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|tmp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|tmp[3] {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.772 ns" { clk clk~clkctrl data_scanC:inst|now_kbclk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.772 ns" { clk {} clk~combout {} clk~clkctrl {} data_scanC:inst|now_kbclk {} } { 0.000ns 0.000ns 0.143ns 0.823ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}