segmain.v

FPGA的PS2口接口程序

module segmain(clk,reset_n,datain,seg_data,seg_com);
input clk;
input reset_n;

input [15:0] datain;
output [7:0]seg_data;
output [3:0]seg_com;

reg [3:0]seg_com;
reg [7:0]seg_data;
reg [3:0]bcd_led;
reg [36:0]count;

always @(posedge clk)
begin
	if(!reset_n)
		count<=0;
	 else
	    count=count+1;
end

always @(count[14:13] or datain)
begin
	case(count[14:13])
		2'b00:
		    begin
		     bcd_led = datain[3:0];
		     seg_com  = 4'b1110;
		    end
		2'b01:
		    begin
		     bcd_led=datain[7:4];
		     seg_com=4'b1101;
		    end
		2'b10:
		    begin
		     bcd_led=datain[11:8];
		     seg_com=4'b1011;
		    end
		2'b11:
		    begin
		     bcd_led=datain[15:12];
		     seg_com=4'b0111;
		    end
	endcase

end

always @(seg_com or bcd_led)
begin
	case(bcd_led)
		4'h0:seg_data=8'hc0;// 0
		4'h1:seg_data=8'hf9;// 1
		4'h2:seg_data=8'ha4;// 2
		4'h3:seg_data=8'hb0;// 3
		4'h4:seg_data=8'h99;// 4
		4'h5:seg_data=8'h92;// 5
		4'h6:seg_data=8'h82;// 6
		4'h7:seg_data=8'hf8;// 7
		4'h8:seg_data=8'h80;// 8
		4'h9:seg_data=8'h90;// 9
		4'ha:seg_data=8'h88;// A
		4'hb:seg_data=8'h83;// b
		4'hc:seg_data=8'hc6;// c
		4'hd:seg_data=8'ha1;// D
		4'he:seg_data=8'h86;// E
		4'hf:seg_data=8'h8e;// F
	 default:seg_data=8'hc0;
  endcase
end

endmodule


/**************************************************************
-- DESCRIPTION   :   BIN to seven segments converter
--                   segment encoding
--                        a
--                      +---+ 
--                    f |   | b
--                      +---+  <- g
--                    e |   | c
--                      +---+
--                        d
--                  Outputs (data_out) active         : low
**************************************************************/