ps2.map.rpt

FPGA的PS2口接口程序

+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                          ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Estimated Total logic elements              ; 185                    ;
;                                             ;                        ;
; Total combinational functions               ; 185                    ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 134                    ;
;     -- 3 input functions                    ; 17                     ;
;     -- <=2 input functions                  ; 34                     ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 171                    ;
;     -- arithmetic mode                      ; 14                     ;
;                                             ;                        ;
; Total registers                             ; 35                     ;
;     -- Dedicated logic registers            ; 35                     ;
;     -- I/O registers                        ; 0                      ;
;                                             ;                        ;
; I/O pins                                    ; 16                     ;
; Maximum fan-out node                        ; data_scanC:inst|PA~434 ;
; Maximum fan-out                             ; 45                     ;
; Total fan-out                               ; 770                    ;
; Average fan-out                             ; 3.26                   ;
+---------------------------------------------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name  ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; |PS2                       ; 185 (0)           ; 35 (0)       ; 0           ; 0            ; 0       ; 0         ; 16   ; 0            ; |PS2                 ; work         ;
;    |convert:inst7|         ; 113 (113)         ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PS2|convert:inst7   ; work         ;
;    |data_scanC:inst|       ; 29 (29)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PS2|data_scanC:inst ; work         ;
;    |segmain:inst8|         ; 43 (43)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |PS2|segmain:inst8   ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------+
; Registers Removed During Synthesis                          ;
+----------------------------------------+--------------------+
; Register name                          ; Reason for Removal ;
+----------------------------------------+--------------------+
; segmain:inst8|count[15..36]            ; Lost fanout        ;
; Total Number of Removed Registers = 22 ;                    ;
+----------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 15    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 15    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; No         ; |PS2|segmain:inst8|Mux3    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Dec 06 14:30:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2
Info: Found 1 design units, including 1 entities, in source file PS2.bdf
    Info: Found entity 1: PS2
Info: Found 1 design units, including 1 entities, in source file data_scanC.v
    Info: Found entity 1: data_scanC
Info: Found 1 design units, including 1 entities, in source file convert.v
    Info: Found entity 1: convert
Info: Found 1 design units, including 1 entities, in source file segmain.v
    Info: Found entity 1: segmain
Info: Elaborating entity "PS2" for the top level hierarchy
Info: Elaborating entity "segmain" for hierarchy "segmain:inst8"
Info: Elaborating entity "data_scanC" for hierarchy "data_scanC:inst"
Info: Elaborating entity "convert" for hierarchy "convert:inst7"
Warning (10208): Verilog HDL Case Statement warning at convert.v(61): honored full_case synthesis attribute - differences between design synthesis and simulation may occur
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "78leddata[7]" is stuck at VCC
Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below.
    Info: Register "segmain:inst8|count[15]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[16]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[17]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[18]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[19]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[20]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[21]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[22]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[23]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[24]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[25]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[26]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[27]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[28]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[29]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[30]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[31]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[32]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[33]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[34]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[35]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst8|count[36]" lost all its fanouts during netlist optimizations.
Info: Implemented 204 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 12 output pins
    Info: Implemented 188 logic cells
Info: Generated suppressed messages file F:/Q80/temp/verilog/EP2C5-V5/PS2_v/PS2.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 160 megabytes
    Info: Processing ended: Sat Dec 06 14:30:34 2008
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/Q80/temp/verilog/EP2C5-V5/PS2_v/PS2.map.smsg.