led_run.v

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module led_run(mclk,led);
input mclk;
output [3:0] led;
reg [3:0] led;
reg [24:0] count;
reg [1:0] state;
wire clk;

always @ (posedge mclk)
count=count+1;
assign clk=count[24];

always @ (posedge clk)
begin
case(state)
2'b00:	led=4'b0001;
2'b01:	led=4'b0010;
2'b10:	led=4'b0100;
2'b11:	led=4'b1000;
endcase
state=state+1;
end
endmodule