ram_control.tan.summary

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.770 ns
From           : rst
To             : rdaddress[2]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.580 ns
From           : RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3
To             : q[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.530 ns
From           : rst
To             : rdaddress[0]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg0
To             : RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------