ram_control.tan.rpt

来自「FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！」· RPT 代码 · 共 335 行 · 第 1/5 页

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4]                                                                                                  ; rdaddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 2.204 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4]                                                                                                  ; rdaddress[1]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 2.204 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4]                                                                                                  ; rdaddress[0]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 2.204 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1]                                                                                                  ; countwr[4]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 2.060 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[0]                                                                                                ; rdaddress[2]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 2.040 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg0 ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg0  ; clk        ; clk      ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2]                                                                                                  ; countwr[4]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.996 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; countwr[4]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.984 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1]                                                                                                  ; countwr[3]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.980 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2]                                                                                                  ; countwr[3]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.916 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; countwr[3]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.904 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2                                                                                                ; countwr[0]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.902 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[0]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg0 ; clk        ; clk      ; None                        ; None                      ; 1.864 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1]                                                                                                  ; countwr[2]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.900 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[2]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.852 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[0]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg0  ; clk        ; clk      ; None                        ; None                      ; 1.849 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wraddress[3]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.845 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[2]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg2  ; clk        ; clk      ; None                        ; None                      ; 1.837 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wraddress[3]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3  ; clk        ; clk      ; None                        ; None                      ; 1.830 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[1]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg1  ; clk        ; clk      ; None                        ; None                      ; 1.830 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; data[1]                                                                                                     ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.823 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[0]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 ; clk        ; clk      ; None                        ; None                      ; 1.811 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[2]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 1.809 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[1]                                                                                                ; rdaddress[2]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.840 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[1]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg1 ; clk        ; clk      ; None                        ; None                      ; 1.797 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[3]                                                                                                ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; countwr[2]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.824 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[2]                                                                                                ; rdaddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.772 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3]                                                                                                  ; countwr[4]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.749 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; countwr[1]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.744 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[0]                                                                                                ; rdaddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[0]                                                                                                ; rdaddress[0]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3]                                                                                                  ; wraddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.297 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2]                                                                                                  ; countwr[2]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.292 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1]                                                                                                  ; countwr[1]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; data[0]                                                                                                      ; clk        ; clk      ; None                        ; None                      ; 1.236 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; state.STATE2                                                                                                ; wren                                                                                                         ; clk        ; clk      ; None                        ; None                      ; 1.171 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[3]                                                                                                  ; countwr[3]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.137 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[0]                                                                                                  ; countwr[0]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.132 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[1]                                                                                                ; rdaddress[1]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.131 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4]                                                                                                  ; countwr[4]                                                                                                   ; clk        ; clk      ; None                        ; None                      ; 1.130 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; wren                                                                                                        ; wren                                                                                                         ; clk        ; clk      ; None                        ; None                      ; 1.103 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[4]                                                                                                  ; state.STATE2                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.070 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[2]                                                                                                  ; data[2]                                                                                                      ; clk        ; clk      ; None                        ; None                      ; 1.059 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[0]                                                                                                ; rdaddress[1]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.057 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countwr[1]                                                                                                  ; data[1]                                                                                                      ; clk        ; clk      ; None                        ; None                      ; 1.047 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[1]                                                                                                ; rdaddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.041 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[2]                                                                                                ; rdaddress[2]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 1.021 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; rdaddress[3]                                                                                                ; rdaddress[3]                                                                                                 ; clk        ; clk      ; None                        ; None                      ; 0.847 ns                ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tsu                                                                ;
+-------+--------------+------------+------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To           ; To Clock ;
+-------+--------------+------------+------+--------------+----------+
; N/A   ; None         ; 6.770 ns   ; rst  ; rdaddress[2] ; clk      ;
; N/A   ; None         ; 6.116 ns   ; rst  ; data[0]      ; clk      ;
; N/A   ; None         ; 6.116 ns   ; rst  ; data[1]      ; clk      ;