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📁 FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！
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123 
defparam \wraddress[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N9
cyclone_lcell \rdaddress[0]~90_I (
// Equation(s):
// \rdaddress[0]~90  = \state.STATE2  # \countwr[4]  & \reduce_nor~22  # !\rst~combout 

	.clk(gnd),
	.dataa(\rst~combout ),
	.datab(\state.STATE2 ),
	.datac(\countwr[4] ),
	.datad(\reduce_nor~22 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\rdaddress[0]~90 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \rdaddress[0]~90_I .operation_mode = "normal";
defparam \rdaddress[0]~90_I .synch_mode = "off";
defparam \rdaddress[0]~90_I .register_cascade_mode = "off";
defparam \rdaddress[0]~90_I .sum_lutc_input = "datac";
defparam \rdaddress[0]~90_I .lut_mask = "FDDD";
defparam \rdaddress[0]~90_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N7
cyclone_lcell \rdaddress[0]~I (
// Equation(s):
// \rdaddress[0]  = DFFEAS(!\rdaddress[0]  & (\rst~combout ), GLOBAL(\clk~combout ), VCC, , \rdaddress[0]~90 , , , , )

	.clk(\clk~combout ),
	.dataa(\rdaddress[0] ),
	.datab(vcc),
	.datac(\rst~combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\rdaddress[0]~90 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\rdaddress[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \rdaddress[0]~I .operation_mode = "normal";
defparam \rdaddress[0]~I .synch_mode = "off";
defparam \rdaddress[0]~I .register_cascade_mode = "off";
defparam \rdaddress[0]~I .sum_lutc_input = "datac";
defparam \rdaddress[0]~I .lut_mask = "5050";
defparam \rdaddress[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N8
cyclone_lcell \rdaddress[1]~I (
// Equation(s):
// \rdaddress[1]  = DFFEAS(\rdaddress[1]  $ \rdaddress[0] , GLOBAL(\clk~combout ), VCC, , \rdaddress[0]~90 , , , !\rst~combout , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\rdaddress[1] ),
	.datac(\rdaddress[0] ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(\rdaddress[0]~90 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\rdaddress[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \rdaddress[1]~I .operation_mode = "normal";
defparam \rdaddress[1]~I .synch_mode = "on";
defparam \rdaddress[1]~I .register_cascade_mode = "off";
defparam \rdaddress[1]~I .sum_lutc_input = "datac";
defparam \rdaddress[1]~I .lut_mask = "3C3C";
defparam \rdaddress[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X16_Y2_N8
cyclone_lcell \rdaddress[2]~I (
// Equation(s):
// \rdaddress[2]  = DFFEAS(\rdaddress[2]  $ (\rdaddress[0]  & \rdaddress[1] ), GLOBAL(\clk~combout ), VCC, , \rdaddress[0]~90 , , , !\rst~combout , )

	.clk(\clk~combout ),
	.dataa(\rdaddress[0] ),
	.datab(\rdaddress[1] ),
	.datac(\rdaddress[2] ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(\rdaddress[0]~90 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\rdaddress[2] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \rdaddress[2]~I .operation_mode = "normal";
defparam \rdaddress[2]~I .synch_mode = "on";
defparam \rdaddress[2]~I .register_cascade_mode = "off";
defparam \rdaddress[2]~I .sum_lutc_input = "datac";
defparam \rdaddress[2]~I .lut_mask = "7878";
defparam \rdaddress[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y2_N5
cyclone_lcell \rdaddress[3]~I (
// Equation(s):
// \rdaddress[3]  = DFFEAS(\rdaddress[3]  $ (\rdaddress[0]  & \rdaddress[2]  & \rdaddress[1] ), GLOBAL(\clk~combout ), VCC, , \rdaddress[0]~90 , , , !\rst~combout , )

	.clk(\clk~combout ),
	.dataa(\rdaddress[0] ),
	.datab(\rdaddress[2] ),
	.datac(\rdaddress[1] ),
	.datad(\rdaddress[3] ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\rst~combout ),
	.sload(gnd),
	.ena(\rdaddress[0]~90 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\rdaddress[3] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \rdaddress[3]~I .operation_mode = "normal";
defparam \rdaddress[3]~I .synch_mode = "on";
defparam \rdaddress[3]~I .register_cascade_mode = "off";
defparam \rdaddress[3]~I .sum_lutc_input = "datac";
defparam \rdaddress[3]~I .lut_mask = "7F80";
defparam \rdaddress[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at M4K_X17_Y2
cyclone_ram_block \RAM_36|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(vcc),
	.portbrewe(vcc),
	.clk0(\clk~combout ),
	.clk1(\clk~combout ),
	.ena0(wren),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\wraddress[3] ,\data[2] ,\data[1] ,\data[0] }),
	.portaaddr({\wraddress[3] ,\data[2] ,\data[1] ,\data[0] }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr({\rdaddress[3] ,\rdaddress[2] ,\rdaddress[1] ,\rdaddress[0] }),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(),
	.portbdataout(\RAM_36|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M4K";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ALTSYNCRAM";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 4;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 4;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 4;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 15;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 4;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 4;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 15;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \RAM_36|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 4;
// synopsys translate_on

// atom is at PIN_87
cyclone_io \q[0]~I (
	.datain(\RAM_36|altsyncram_component|auto_generated|q_b[0] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(q[0]));
// synopsys translate_off
defparam \q[0]~I .operation_mode = "output";
defparam \q[0]~I .input_register_mode = "none";
defparam \q[0]~I .output_register_mode = "none";
defparam \q[0]~I .oe_register_mode = "none";
defparam \q[0]~I .input_async_reset = "none";
defparam \q[0]~I .output_async_reset = "none";
defparam \q[0]~I .oe_async_reset = "none";
defparam \q[0]~I .input_sync_reset = "none";
defparam \q[0]~I .output_sync_reset = "none";
defparam \q[0]~I .oe_sync_reset = "none";
defparam \q[0]~I .input_power_up = "low";
defparam \q[0]~I .output_power_up = "low";
defparam \q[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_88
cyclone_io \q[1]~I (
	.datain(\RAM_36|altsyncram_component|auto_generated|q_b[1] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(q[1]));
// synopsys translate_off
defparam \q[1]~I .operation_mode = "output";
defparam \q[1]~I .input_register_mode = "none";
defparam \q[1]~I .output_register_mode = "none";
defparam \q[1]~I .oe_register_mode = "none";
defparam \q[1]~I .input_async_reset = "none";
defparam \q[1]~I .output_async_reset = "none";
defparam \q[1]~I .oe_async_reset = "none";
defparam \q[1]~I .input_sync_reset = "none";
defparam \q[1]~I .output_sync_reset = "none";
defparam \q[1]~I .oe_sync_reset = "none";
defparam \q[1]~I .input_power_up = "low";
defparam \q[1]~I .output_power_up = "low";
defparam \q[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_95
cyclone_io \q[2]~I (
	.datain(\RAM_36|altsyncram_component|auto_generated|q_b[2] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(q[2]));
// synopsys translate_off
defparam \q[2]~I .operation_mode = "output";
defparam \q[2]~I .input_register_mode = "none";
defparam \q[2]~I .output_register_mode = "none";
defparam \q[2]~I .oe_register_mode = "none";
defparam \q[2]~I .input_async_reset = "none";
defparam \q[2]~I .output_async_reset = "none";
defparam \q[2]~I .oe_async_reset = "none";
defparam \q[2]~I .input_sync_reset = "none";
defparam \q[2]~I .output_sync_reset = "none";
defparam \q[2]~I .oe_sync_reset = "none";
defparam \q[2]~I .input_power_up = "low";
defparam \q[2]~I .output_power_up = "low";
defparam \q[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_94
cyclone_io \q[3]~I (
	.datain(\RAM_36|altsyncram_component|auto_generated|q_b[3] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(q[3]));
// synopsys translate_off
defparam \q[3]~I .operation_mode = "output";
defparam \q[3]~I .input_register_mode = "none";
defparam \q[3]~I .output_register_mode = "none";
defparam \q[3]~I .oe_register_mode = "none";
defparam \q[3]~I .input_async_reset = "none";
defparam \q[3]~I .output_async_reset = "none";
defparam \q[3]~I .oe_async_reset = "none";
defparam \q[3]~I .input_sync_reset = "none";
defparam \q[3]~I .output_sync_reset = "none";
defparam \q[3]~I .oe_sync_reset = "none";
defparam \q[3]~I .input_power_up = "low";
defparam \q[3]~I .output_power_up = "low";
defparam \q[3]~I .oe_power_up = "low";
// synopsys translate_on

endmodule
123

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