📄 ram_control.tan.qmsg

📁 FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3 memory RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3\" and destination memory \"RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3 1 MEM M4K_X17_Y2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3 2 MEM M4K_X17_Y2 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y2; Fanout = 0; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "4.319 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "4.319 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.907 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.708 ns) 2.907 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3 2 MEM M4K_X17_Y2 0 " "Info: 2: + IC(0.730 ns) + CELL(0.708 ns) = 2.907 ns; Loc. = M4K_X17_Y2; Fanout = 0; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_memory_reg3'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "1.438 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 74.89 % " "Info: Total cell delay = 2.177 ns ( 74.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.11 % " "Info: Total interconnect delay = 0.730 ns ( 25.11 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.907 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.907 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.921 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.722 ns) 2.921 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3 2 MEM M4K_X17_Y2 1 " "Info: 2: + IC(0.730 ns) + CELL(0.722 ns) = 2.921 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~porta_datain_reg3'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "1.452 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 75.01 % " "Info: Total cell delay = 2.191 ns ( 75.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 24.99 % " "Info: Total interconnect delay = 0.730 ns ( 24.99 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.921 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.907 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.907 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.708ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.921 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "4.319 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.907 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.907 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.708ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.921 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "rdaddress\[2\] rst clk 6.770 ns register " "Info: tsu for register \"rdaddress\[2\]\" (data pin = \"rst\", clock pin = \"clk\") is 6.770 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.636 ns + Longest pin register " "Info: + Longest pin to register delay is 9.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rst 1 PIN PIN_85 18 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_85; Fanout = 18; PIN Node = 'rst'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { rst } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.479 ns) + CELL(0.590 ns) 7.544 ns rdaddress\[0\]~90 2 COMB LC_X14_Y2_N9 4 " "Info: 2: + IC(5.479 ns) + CELL(0.590 ns) = 7.544 ns; Loc. = LC_X14_Y2_N9; Fanout = 4; COMB Node = 'rdaddress\[0\]~90'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "6.069 ns" { rst rdaddress[0]~90 } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.225 ns) + CELL(0.867 ns) 9.636 ns rdaddress\[2\] 3 REG LC_X16_Y2_N8 3 " "Info: 3: + IC(1.225 ns) + CELL(0.867 ns) = 9.636 ns; Loc. = LC_X16_Y2_N8; Fanout = 3; REG Node = 'rdaddress\[2\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.092 ns" { rdaddress[0]~90 rdaddress[2] } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.932 ns 30.43 % " "Info: Total cell delay = 2.932 ns ( 30.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.704 ns 69.57 % " "Info: Total interconnect delay = 6.704 ns ( 69.57 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "9.636 ns" { rst rdaddress[0]~90 rdaddress[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.636 ns" { rst rst~out0 rdaddress[0]~90 rdaddress[2] } { 0.000ns 0.000ns 5.479ns 1.225ns } { 0.000ns 1.475ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns rdaddress\[2\] 2 REG LC_X16_Y2_N8 3 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y2_N8; Fanout = 3; REG Node = 'rdaddress\[2\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "1.434 ns" { clk rdaddress[2] } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.903 ns" { clk rdaddress[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 rdaddress[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "9.636 ns" { rst rdaddress[0]~90 rdaddress[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.636 ns" { rst rst~out0 rdaddress[0]~90 rdaddress[2] } { 0.000ns 0.000ns 5.479ns 1.225ns } { 0.000ns 1.475ns 0.590ns 0.867ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.903 ns" { clk rdaddress[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 rdaddress[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0 11.580 ns memory " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through memory \"RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0\" is 11.580 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.917 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.718 ns) 2.917 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0 2 MEM M4K_X17_Y2 4 " "Info: 2: + IC(0.730 ns) + CELL(0.718 ns) = 2.917 ns; Loc. = M4K_X17_Y2; Fanout = 4; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "1.448 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns 74.97 % " "Info: Total cell delay = 2.187 ns ( 74.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.03 % " "Info: Total interconnect delay = 0.730 ns ( 25.03 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.917 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.718ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.013 ns + Longest memory pin " "Info: + Longest memory to pin delay is 8.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X17_Y2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y2; Fanout = 4; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|q_b\[0\] 2 MEM M4K_X17_Y2 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\|q_b\[0\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "4.317 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] } "NODE_NAME" } "" } } { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/db/altsyncram_e181.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(2.108 ns) 8.013 ns q\[0\] 3 PIN PIN_87 0 " "Info: 3: + IC(1.588 ns) + CELL(2.108 ns) = 8.013 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "3.696 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] q[0] } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.425 ns 80.18 % " "Info: Total cell delay = 6.425 ns ( 80.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns 19.82 % " "Info: Total interconnect delay = 1.588 ns ( 19.82 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "8.013 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.013 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] q[0] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 4.317ns 2.108ns } } }  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.917 ns" { clk RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.718ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "8.013 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.013 ns" { RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] q[0] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 4.317ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "rdaddress\[0\] rst clk -4.530 ns register " "Info: th for register \"rdaddress\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is -4.530 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns rdaddress\[0\] 2 REG LC_X14_Y2_N7 5 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y2_N7; Fanout = 5; REG Node = 'rdaddress\[0\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "1.434 ns" { clk rdaddress[0] } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.903 ns" { clk rdaddress[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 rdaddress[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.448 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rst 1 PIN PIN_85 18 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_85; Fanout = 18; PIN Node = 'rst'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { rst } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.495 ns) + CELL(0.478 ns) 7.448 ns rdaddress\[0\] 2 REG LC_X14_Y2_N7 5 " "Info: 2: + IC(5.495 ns) + CELL(0.478 ns) = 7.448 ns; Loc. = LC_X14_Y2_N7; Fanout = 5; REG Node = 'rdaddress\[0\]'" {  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "5.973 ns" { rst rdaddress[0] } "NODE_NAME" } "" } } { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 26.22 % " "Info: Total cell delay = 1.953 ns ( 26.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.495 ns 73.78 % " "Info: Total interconnect delay = 5.495 ns ( 73.78 % )" {  } {  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "7.448 ns" { rst rdaddress[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.448 ns" { rst rst~out0 rdaddress[0] } { 0.000ns 0.000ns 5.495ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}  } { { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "2.903 ns" { clk rdaddress[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 rdaddress[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "7.448 ns" { rst rdaddress[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.448 ns" { rst rst~out0 rdaddress[0] } { 0.000ns 0.000ns 5.495ns } { 0.000ns 1.475ns 0.478ns } } }  } 0}
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