ram_control_v.sdo

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        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE data\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (5479:5479:5479) (5590:5590:5590))
        (PORT datad (743:743:743) (750:750:750))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE data\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1656:1656:1656) (1694:1694:1694))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE wraddress\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5474:5474:5474) (5568:5568:5568))
        (PORT datac (798:798:798) (819:819:819))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE wraddress\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1656:1656:1656) (1694:1694:1694))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rdaddress\[0\]\~90_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5373:5373:5373) (5479:5479:5479))
        (PORT datab (1086:1086:1086) (1140:1140:1140))
        (PORT datac (538:538:538) (562:562:562))
        (PORT datad (424:424:424) (429:429:429))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rdaddress\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (562:562:562) (562:562:562))
        (PORT datac (5372:5372:5372) (5495:5495:5495))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE rdaddress\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1297:1297:1297) (1350:1350:1350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rdaddress\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (517:517:517) (524:524:524))
        (PORT datac (560:560:560) (579:579:579))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE rdaddress\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1297:1297:1297) (1350:1350:1350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rdaddress\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1267:1267:1267) (1302:1302:1302))
        (PORT datab (1200:1200:1200) (1233:1233:1233))
        (PORT datac (512:512:512) (543:543:543))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE rdaddress\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6504:6504:6504) (6665:6665:6665))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1993:1993:1993) (2092:2092:2092))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE rdaddress\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (562:562:562) (562:562:562))
        (PORT datab (1141:1141:1141) (1165:1165:1165))
        (PORT datac (537:537:537) (563:563:563))
        (PORT datad (536:536:536) (538:538:538))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE rdaddress\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1297:1297:1297) (1350:1350:1350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1796:1796:1796) (1849:1849:1849))
        (PORT d[1] (1765:1765:1765) (1830:1830:1830))
        (PORT d[2] (1772:1772:1772) (1837:1837:1837))
        (PORT d[3] (1765:1765:1765) (1830:1830:1830))
        (PORT clk (1452:1452:1452) (1434:1434:1434))
        (PORT ena (1898:1898:1898) (1964:1964:1964))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (93:93:93))
      (SETUP ena (posedge clk) (93:93:93))
      (HOLD d (posedge clk) (55:55:55))
      (HOLD ena (posedge clk) (55:55:55))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1809:1809:1809) (1864:1864:1864))
        (PORT d[1] (1755:1755:1755) (1823:1823:1823))
        (PORT d[2] (1785:1785:1785) (1852:1852:1852))
        (PORT d[3] (1780:1780:1780) (1845:1845:1845))
        (PORT clk (1452:1452:1452) (1434:1434:1434))
        (PORT ena (1898:1898:1898) (1964:1964:1964))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (93:93:93))
      (SETUP ena (posedge clk) (93:93:93))
      (HOLD d (posedge clk) (55:55:55))
      (HOLD ena (posedge clk) (55:55:55))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (427:427:427) (427:427:427))
        (PORT clk (1452:1452:1452) (1434:1434:1434))
        (PORT ena (1898:1898:1898) (1964:1964:1964))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (93:93:93))
      (SETUP ena (posedge clk) (93:93:93))
      (HOLD d (posedge clk) (55:55:55))
      (HOLD ena (posedge clk) (55:55:55))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1452:1452:1452) (1452:1452:1452))
        (PORT d[0] (1898:1898:1898) (1898:1898:1898))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_pulse_generator")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2102:2102:2102) (2084:2084:2084))
        (IOPATH (posedge clk) pulse (0:0:0) (2411:2411:2411))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_pulse_generator")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2102:2102:2102) (2084:2084:2084))
        (IOPATH (posedge clk) pulse (0:0:0) (2936:2936:2936))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1744:1744:1744) (1811:1811:1811))
        (PORT d[1] (1742:1742:1742) (1797:1797:1797))
        (PORT d[2] (1783:1783:1783) (1809:1809:1809))
        (PORT d[3] (1720:1720:1720) (1789:1789:1789))
        (PORT clk (1448:1448:1448) (1430:1430:1430))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (93:93:93))
      (HOLD d (posedge clk) (55:55:55))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.rewe_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (404:404:404) (404:404:404))
        (PORT clk (1419:1419:1419) (1401:1401:1401))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (93:93:93))
      (HOLD d (posedge clk) (55:55:55))
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_register")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.active_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1448:1448:1448) (1430:1430:1430))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_ram_pulse_generator")
    (INSTANCE RAM_36\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (2098:2098:2098) (2080:2080:2080))
        (IOPATH (posedge clk) pulse (0:0:0) (4317:4317:4317))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE q\[0\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1336:1336:1336) (1588:1588:1588))
        (IOPATH datain padio (2108:2108:2108) (2108:2108:2108))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE q\[1\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1107:1107:1107) (1357:1357:1357))
        (IOPATH datain padio (2108:2108:2108) (2108:2108:2108))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE q\[2\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1314:1314:1314) (1564:1564:1564))
        (IOPATH datain padio (2108:2108:2108) (2108:2108:2108))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE q\[3\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (994:994:994) (1242:1242:1242))
        (IOPATH datain padio (2108:2108:2108) (2108:2108:2108))
      )
    )
  )
)