ram_control.flow.rpt

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Flow report for ram_control
Sat Jul 29 11:10:31 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------+-----------------------------------------------+
; Flow Status             ; Successful - Sat Jul 29 11:10:31 2006         ;
; Quartus II Version      ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name           ; ram_control                                   ;
; Top-level Entity Name   ; ram_control                                   ;
; Family                  ; Cyclone                                       ;
; Device                  ; EP1C6Q240C8                                   ;
; Timing Models           ; Final                                         ;
; Met timing requirements ; Yes                                           ;
; Total logic elements    ; 21 / 5,980 ( < 1 % )                          ;
; Total pins              ; 6 / 185 ( 3 % )                               ;
; Total virtual pins      ; 0                                             ;
; Total memory bits       ; 64 / 92,160 ( < 1 % )                         ;
; Total PLLs              ; 0 / 2 ( 0 % )                                 ;
+-------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 07/29/2006 11:10:09 ;
; Main task         ; Compilation         ;
; Revision Name     ; ram_control         ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:04     ;
; Fitter               ; 00:00:07     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:01     ;
; EDA Netlist Writer   ; 00:00:02     ;
; Total                ; 00:00:16     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off ram_control -c ram_control
quartus_fit --read_settings_files=off --write_settings_files=off ram_control -c ram_control
quartus_asm --read_settings_files=off --write_settings_files=off ram_control -c ram_control
quartus_tan --read_settings_files=off --write_settings_files=off ram_control -c ram_control --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off ram_control -c ram_control