ram_control.map.qmsg

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 29 11:10:09 2006 " "Info: Processing started: Sat Jul 29 11:10:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ram_control -c ram_control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram_control -c ram_control" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_36.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM_36.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM_36 " "Info: Found entity 1: RAM_36" {  } { { "RAM_36.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "wrclock ram_control.v(15) " "Warning: Verilog HDL net warning at ram_control.v(15): created undeclared net \"wrclock\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "rdclock ram_control.v(16) " "Warning: Verilog HDL net warning at ram_control.v(16): created undeclared net \"rdclock\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 16 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_control " "Info: Found entity 1: ram_control" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram_control " "Info: Elaborating entity \"ram_control\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ram_control.v(21) " "Warning: Verilog HDL assignment warning at ram_control.v(21): truncated value with size 32 to match size of target (4)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 ram_control.v(34) " "Warning: Verilog HDL assignment warning at ram_control.v(34): truncated value with size 5 to match size of target (4)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ram_control.v(38) " "Warning: Verilog HDL assignment warning at ram_control.v(38): truncated value with size 32 to match size of target (1)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ram_control.v(43) " "Warning: Verilog HDL assignment warning at ram_control.v(43): truncated value with size 32 to match size of target (1)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ram_control.v(44) " "Warning: Verilog HDL assignment warning at ram_control.v(44): truncated value with size 32 to match size of target (4)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ram_control.v(50) " "Warning: Verilog HDL assignment warning at ram_control.v(50): truncated value with size 32 to match size of target (4)" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 50 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_36 RAM_36:RAM_36 " "Info: Elaborating entity \"RAM_36\" for hierarchy \"RAM_36:RAM_36\"" {  } { { "ram_control.v" "RAM_36" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 55 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram RAM_36:RAM_36\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"RAM_36:RAM_36\|altsyncram:altsyncram_component\"" {  } { { "RAM_36.v" "altsyncram_component" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v" 79 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_e181.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e181.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_e181 " "Info: Found entity 1: altsyncram_e181" {  } { { "db/altsyncram_e181.tdf" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/db/altsyncram_e181.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_e181 RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated " "Info: Elaborating entity \"altsyncram_e181\" for hierarchy \"RAM_36:RAM_36\|altsyncram:altsyncram_component\|altsyncram_e181:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "wraddress\[2\] data\[2\] " "Info: Duplicate register \"wraddress\[2\]\" merged to single register \"data\[2\]\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "wraddress\[1\] data\[1\] " "Info: Duplicate register \"wraddress\[1\]\" merged to single register \"data\[1\]\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "wraddress\[0\] data\[0\] " "Info: Duplicate register \"wraddress\[0\]\" merged to single register \"data\[0\]\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 8 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[3\] wraddress\[3\] " "Info: Duplicate register \"data\[3\]\" merged to single register \"wraddress\[3\]\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|ram_control\|state 2 0 " "Info: State machine \"\|ram_control\|state\" contains 2 states and 0 state bits" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|ram_control\|state " "Info: Selected Auto state machine encoding method for state machine \"\|ram_control\|state\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|ram_control\|state " "Info: Encoding result for state machine \"\|ram_control\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "1 " "Info: Completed encoding using 1 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.STATE2 " "Info: Encoded state bit \"state.STATE2\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ram_control\|state.STATE1 0 " "Info: State \"\|ram_control\|state.STATE1\" uses code string \"0\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|ram_control\|state.STATE2 1 " "Info: State \"\|ram_control\|state.STATE2\" uses code string \"1\"" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0}  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v" 11 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "31 " "Info: Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 29 11:10:12 2006 " "Info: Processing ended: Sat Jul 29 11:10:12 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}