ram_control.hier_info

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|ram_control
q[0] <= RAM_36:RAM_36.q
q[1] <= RAM_36:RAM_36.q
q[2] <= RAM_36:RAM_36.q
q[3] <= RAM_36:RAM_36.q
clk => rdclock.IN2
rst => data~8.OUTPUTSELECT
rst => data~9.OUTPUTSELECT
rst => data~10.OUTPUTSELECT
rst => data~11.OUTPUTSELECT
rst => wren~3.OUTPUTSELECT
rst => wraddress~8.OUTPUTSELECT
rst => wraddress~9.OUTPUTSELECT
rst => wraddress~10.OUTPUTSELECT
rst => wraddress~11.OUTPUTSELECT
rst => rdaddress~16.OUTPUTSELECT
rst => rdaddress~17.OUTPUTSELECT
rst => rdaddress~18.OUTPUTSELECT
rst => rdaddress~19.OUTPUTSELECT
rst => countwr~5.OUTPUTSELECT
rst => countwr~6.OUTPUTSELECT
rst => countwr~7.OUTPUTSELECT
rst => countwr~8.OUTPUTSELECT
rst => countwr~9.OUTPUTSELECT
rst => state~6.OUTPUTSELECT
rst => state~7.OUTPUTSELECT


|ram_control|RAM_36:RAM_36
data[0] => data[0]~3.IN1
data[1] => data[1]~2.IN1
data[2] => data[2]~1.IN1
data[3] => data[3]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~3.IN1
wraddress[1] => wraddress[1]~2.IN1
wraddress[2] => wraddress[2]~1.IN1
wraddress[3] => wraddress[3]~0.IN1
rdaddress[0] => rdaddress[0]~3.IN1
rdaddress[1] => rdaddress[1]~2.IN1
rdaddress[2] => rdaddress[2]~1.IN1
rdaddress[3] => rdaddress[3]~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b


|ram_control|RAM_36:RAM_36|altsyncram:altsyncram_component
wren_a => altsyncram_e181:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_e181:auto_generated.data_a[0]
data_a[1] => altsyncram_e181:auto_generated.data_a[1]
data_a[2] => altsyncram_e181:auto_generated.data_a[2]
data_a[3] => altsyncram_e181:auto_generated.data_a[3]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
address_a[0] => altsyncram_e181:auto_generated.address_a[0]
address_a[1] => altsyncram_e181:auto_generated.address_a[1]
address_a[2] => altsyncram_e181:auto_generated.address_a[2]
address_a[3] => altsyncram_e181:auto_generated.address_a[3]
address_b[0] => altsyncram_e181:auto_generated.address_b[0]
address_b[1] => altsyncram_e181:auto_generated.address_b[1]
address_b[2] => altsyncram_e181:auto_generated.address_b[2]
address_b[3] => altsyncram_e181:auto_generated.address_b[3]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_e181:auto_generated.clock0
clock1 => altsyncram_e181:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_b[0] <= altsyncram_e181:auto_generated.q_b[0]
q_b[1] <= altsyncram_e181:auto_generated.q_b[1]
q_b[2] <= altsyncram_e181:auto_generated.q_b[2]
q_b[3] <= altsyncram_e181:auto_generated.q_b[3]


|ram_control|RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0