ram_control.eda.qmsg

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 29 11:10:29 2006 " "Info: Processing started: Sat Jul 29 11:10:29 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ram_control -c ram_control " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ram_control -c ram_control" {  } {  } 0}
{ "Info" "IBASEO_DONE_HDL_SDO_GENERATION" "ram_control.vo ram_control_v.sdo E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/ simulation " "Info: Generated files \"ram_control.vo\" and \"ram_control_v.sdo\" in directory \"E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 29 11:10:31 2006 " "Info: Processing ended: Sat Jul 29 11:10:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}