ram_control.tan.rpt

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Jul 29 11:10:26 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ram_control -c ram_control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 197.01 MHz between source memory "RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3" and destination memory "RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3" (period= 5.076 ns)
    Info: + Longest memory to memory delay is 4.319 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3'
        Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y2; Fanout = 0; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3'
        Info: Total cell delay = 4.319 ns ( 100.00 % )
    Info: - Smallest clock skew is -0.014 ns
        Info: + Shortest clock path from clock "clk" to destination memory is 2.907 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'
            Info: 2: + IC(0.730 ns) + CELL(0.708 ns) = 2.907 ns; Loc. = M4K_X17_Y2; Fanout = 0; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_memory_reg3'
            Info: Total cell delay = 2.177 ns ( 74.89 % )
            Info: Total interconnect delay = 0.730 ns ( 25.11 % )
        Info: - Longest clock path from clock "clk" to source memory is 2.921 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'
            Info: 2: + IC(0.730 ns) + CELL(0.722 ns) = 2.921 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~porta_datain_reg3'
            Info: Total cell delay = 2.191 ns ( 75.01 % )
            Info: Total interconnect delay = 0.730 ns ( 24.99 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Micro setup delay of destination is 0.093 ns
Info: tsu for register "rdaddress[2]" (data pin = "rst", clock pin = "clk") is 6.770 ns
    Info: + Longest pin to register delay is 9.636 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_85; Fanout = 18; PIN Node = 'rst'
        Info: 2: + IC(5.479 ns) + CELL(0.590 ns) = 7.544 ns; Loc. = LC_X14_Y2_N9; Fanout = 4; COMB Node = 'rdaddress[0]~90'
        Info: 3: + IC(1.225 ns) + CELL(0.867 ns) = 9.636 ns; Loc. = LC_X16_Y2_N8; Fanout = 3; REG Node = 'rdaddress[2]'
        Info: Total cell delay = 2.932 ns ( 30.43 % )
        Info: Total interconnect delay = 6.704 ns ( 69.57 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X16_Y2_N8; Fanout = 3; REG Node = 'rdaddress[2]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "clk" to destination pin "q[0]" through memory "RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0" is 11.580 ns
    Info: + Longest clock path from clock "clk" to source memory is 2.917 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'
        Info: 2: + IC(0.730 ns) + CELL(0.718 ns) = 2.917 ns; Loc. = M4K_X17_Y2; Fanout = 4; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0'
        Info: Total cell delay = 2.187 ns ( 74.97 % )
        Info: Total interconnect delay = 0.730 ns ( 25.03 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 8.013 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y2; Fanout = 4; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y2; Fanout = 1; MEM Node = 'RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0]'
        Info: 3: + IC(1.588 ns) + CELL(2.108 ns) = 8.013 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'q[0]'
        Info: Total cell delay = 6.425 ns ( 80.18 % )
        Info: Total interconnect delay = 1.588 ns ( 19.82 % )
Info: th for register "rdaddress[0]" (data pin = "rst", clock pin = "clk") is -4.530 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 31; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y2_N7; Fanout = 5; REG Node = 'rdaddress[0]'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.448 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_85; Fanout = 18; PIN Node = 'rst'
        Info: 2: + IC(5.495 ns) + CELL(0.478 ns) = 7.448 ns; Loc. = LC_X14_Y2_N7; Fanout = 5; REG Node = 'rdaddress[0]'
        Info: Total cell delay = 1.953 ns ( 26.22 % )
        Info: Total interconnect delay = 5.495 ns ( 73.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 29 11:10:27 2006
    Info: Elapsed time: 00:00:01