ram_control.tan.rpt

来自「FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！」· RPT 代码 · 共 335 行 · 第 1/5 页

; N/A   ; None         ; 6.116 ns   ; rst  ; data[2]      ; clk      ;
; N/A   ; None         ; 6.116 ns   ; rst  ; wraddress[3] ; clk      ;
; N/A   ; None         ; 6.044 ns   ; rst  ; state.STATE2 ; clk      ;
; N/A   ; None         ; 6.028 ns   ; rst  ; rdaddress[0] ; clk      ;
; N/A   ; None         ; 6.028 ns   ; rst  ; rdaddress[1] ; clk      ;
; N/A   ; None         ; 6.028 ns   ; rst  ; rdaddress[3] ; clk      ;
; N/A   ; None         ; 5.274 ns   ; rst  ; wren         ; clk      ;
; N/A   ; None         ; 5.246 ns   ; rst  ; countwr[0]   ; clk      ;
; N/A   ; None         ; 5.246 ns   ; rst  ; countwr[1]   ; clk      ;
; N/A   ; None         ; 5.246 ns   ; rst  ; countwr[4]   ; clk      ;
; N/A   ; None         ; 5.246 ns   ; rst  ; countwr[2]   ; clk      ;
; N/A   ; None         ; 5.246 ns   ; rst  ; countwr[3]   ; clk      ;
+-------+--------------+------------+------+--------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                  ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                                         ; To   ; From Clock ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 11.580 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 ; q[0] ; clk        ;
; N/A   ; None         ; 11.580 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg1 ; q[0] ; clk        ;
; N/A   ; None         ; 11.580 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg2 ; q[0] ; clk        ;
; N/A   ; None         ; 11.580 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3 ; q[0] ; clk        ;
; N/A   ; None         ; 11.556 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 ; q[2] ; clk        ;
; N/A   ; None         ; 11.556 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg1 ; q[2] ; clk        ;
; N/A   ; None         ; 11.556 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg2 ; q[2] ; clk        ;
; N/A   ; None         ; 11.556 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3 ; q[2] ; clk        ;
; N/A   ; None         ; 11.349 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 ; q[1] ; clk        ;
; N/A   ; None         ; 11.349 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg1 ; q[1] ; clk        ;
; N/A   ; None         ; 11.349 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg2 ; q[1] ; clk        ;
; N/A   ; None         ; 11.349 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3 ; q[1] ; clk        ;
; N/A   ; None         ; 11.234 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg0 ; q[3] ; clk        ;
; N/A   ; None         ; 11.234 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg1 ; q[3] ; clk        ;
; N/A   ; None         ; 11.234 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg2 ; q[3] ; clk        ;
; N/A   ; None         ; 11.234 ns  ; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ram_block1a0~portb_address_reg3 ; q[3] ; clk        ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------------------------+------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To           ; To Clock ;
+---------------+-------------+-----------+------+--------------+----------+
; N/A           ; None        ; -4.530 ns ; rst  ; rdaddress[0] ; clk      ;
; N/A           ; None        ; -4.613 ns ; rst  ; data[1]      ; clk      ;
; N/A           ; None        ; -4.623 ns ; rst  ; state.STATE2 ; clk      ;
; N/A           ; None        ; -4.625 ns ; rst  ; data[2]      ; clk      ;
; N/A           ; None        ; -4.863 ns ; rst  ; data[0]      ; clk      ;
; N/A           ; None        ; -4.863 ns ; rst  ; wraddress[3] ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; countwr[0]   ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; rdaddress[1] ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; rdaddress[3] ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; countwr[1]   ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; countwr[4]   ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; countwr[2]   ; clk      ;
; N/A           ; None        ; -5.194 ns ; rst  ; countwr[3]   ; clk      ;
; N/A           ; None        ; -5.222 ns ; rst  ; wren         ; clk      ;
; N/A           ; None        ; -5.222 ns ; rst  ; rdaddress[2] ; clk      ;
+---------------+-------------+-----------+------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer